Overview

Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted hardware description language (HDL) that embeds hardware design inside the Scala programming language [Tywaves paper]. By being embedded in Scala, Chisel brings object-oriented and functional programming, type safety, and parameterization to hardware design, while still targeting synthesizable RTL.

Language Features and Design Philosophy

Chisel's main contribution is providing modern software-language constructs to hardware authors:

• Object-oriented and functional programming constructs directly available within hardware descriptions [Tywaves paper].
• Type safety, which is intended to catch errors at compile time rather than during simulation or synthesis [Tywaves paper].
• Parameterization, enabling reusable and configurable hardware modules [Tywaves paper].

The language is "broadly adopted" within both academia and industry, particularly in the RISC-V ecosystem [Tywaves paper].

Compilation and Tooling

Chisel designs are compiled to lower-level RTL representations for synthesis and simulation. The Tywaves project notes that Chisel designs can flow through the CIRCT MLIR compiler, which provides a typed intermediate representation that can preserve some of the higher-level type information that would otherwise be lost during translation to Verilog [Tywaves paper].

Chisel also provides a blackbox mechanism — a way to instantiate external modules — which allows designs described in any HDL to interoperate with Chisel code. ChiselVerify explicitly leverages Chisel blackboxes to remain HDL-agnostic at the verification boundary [ChiselVerify paper].

Notable Designs Written in Chisel

Chisel is the implementation language of several prominent open-source RISC-V processor cores:

• Rocket: a five-stage, single-issue, in-order scalar RISC-V processor, which was the first RISC-V processor open-sourced by UC Berkeley and supports extensions such as hypervisor and cryptography [MorFuzz paper].
• BOOM (Berkeley Out-of-Order Machine): a third-generation out-of-order superscalar RISC-V processor, also written in Chisel, with a sophisticated microarchitecture that has been verified on FPGA [MorFuzz paper].

Both Rocket and BOOM are written in Chisel and are maintained within the RISC-V community [MorFuzz paper].

Constructs Used by Downstream Tools

Downstream research tools interact with specific Chisel constructs:

• The Chisel Vec constructor generates register arrays that are recognized by tools such as DejaVuzz. By default, DejaVuzz treats all register arrays — including those generated by the Chisel Vec constructor — as potential sinks for its differential information-flow tracking instrumentation [DejaVuzz paper].
• Chisel blackboxes are used by ChiselVerify to wrap non-Chisel HDL modules inside a Chisel-based verification environment [ChiselVerify paper].

Verification Ecosystem (ChiselVerify)

ChiselVerify is an open-source verification framework built on top of Chisel and Scala. It is intended for verifying circuits described in any HDL by leveraging Chisel blackboxes, and exposes SystemVerilog-inspired features such as functional coverage, constrained-random verification, bus functional models, and transaction-level modeling, all within a Scala-driven testing environment inspired by the Universal Verification Methodology (UVM) [ChiselVerify paper].

Debugging Challenges

Although Chisel's higher-level language features improve authoring, they introduce a debuggability gap. When designs are translated down to Verilog and simulated, type information and data-structure hierarchies are lost in the translation, simulator output, and waveform viewers [Tywaves paper]. The Tywaves project addresses this by introducing a typed waveform format that bridges Chisel source-level types into the Surfer waveform viewer, with contributions to the Chisel library and CIRCT MLIR compiler [Tywaves paper].

Role in RISC-V Hardware Fuzzing

Chisel-written cores such as Rocket and BOOM are common targets for hardware-level fuzzing research. For example, MorFuzz evaluates three RISC-V cores (CVA6 written in SystemVerilog, plus Rocket and BOOM written in Chisel) to demonstrate compatibility across different RISC-V microarchitectures [MorFuzz paper]. DejaVuzz similarly evaluates BOOM and XiangShan, and explicitly accounts for register arrays generated by the Chisel Vec constructor when identifying potential sinks for information-flow tracking [DejaVuzz paper].

Related Concepts

• DejaVuzz — a hardware fuzzer that explicitly handles register arrays generated by the Chisel Vec constructor when instrumenting RTL [DejaVuzz paper].
• ChiselVerify — a verification framework built on top of Chisel [ChiselVerify paper].
• Tywaves — a typed waveform viewer that extends the Chisel library and CIRCT MLIR compiler [Tywaves paper].
• CIRCT MLIR compiler — the compiler infrastructure used in conjunction with Chisel for downstream tooling [Tywaves paper].
• Rocket — RISC-V processor implemented in Chisel [MorFuzz paper].
• BOOM — Berkeley Out-of-Order Machine, implemented in Chisel [MorFuzz paper].