AIGER
ConceptAIGER is a formal hardware description language that represents hardware systems at the bit level using and-inverter graphs (AIGs). It is commonly used as a gate-level netlist format in logic synthesis, as a benchmark format for safety specifications in reactive synthesis competitions, and as an output backend of the Yosys synthesis toolchain.
WIKI
Overview
AIGER is a formal language used to describe hardware systems at the bit level. According to the µArchiFI paper (Tollec et al., 2023), AIGER describes hardware systems using an and-inverter graph [1]. This makes AIGER a foundational format for representing combinational and sequential digital circuits in a compact, canonical form.
Role in Logic Synthesis
NEIGHBORHOOD
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