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AIGER

Concept

AIGER is a formal hardware description language that represents hardware systems at the bit level using and-inverter graphs (AIGs). It is commonly used as a gate-level netlist format in logic synthesis, as a benchmark format for safety specifications in reactive synthesis competitions, and as an output backend of the Yosys synthesis toolchain.

First seen 7/6/2026
Last seen 7/6/2026
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Overview

AIGER is a formal language used to describe hardware systems at the bit level. According to the µArchiFI paper (Tollec et al., 2023), AIGER describes hardware systems using an and-inverter graph [1]. This makes AIGER a foundational format for representing combinational and sequential digital circuits in a compact, canonical form.

Role in Logic Synthesis

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NEIGHBORHOOD

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RELATIONSHIPS

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Yosys ← uses 100% 1e
Yosys can produce AIGER output format.

CITATIONS

5 sources
5 citations — click to expand
[1] AIGER describes hardware systems at the bit level using an and-inverter graph. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
[2] AIGER is one of the formal languages supported as a backend output of the Yosys open-source synthesis framework, alongside SMV, BTOR2, and SMT-LIB. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
[3] BTOR2 is a word-level generalization of AIGER providing word-level data types, registers, and memories. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
[4] AIGER is a gate-level netlist format used in logic synthesis, and is targeted by specialized fuzz testing and delta debugging toolkits. An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
[5] AIGER-based format is used in SYNTCOMP for safety specifications, with the SYNTCOMP 2016 edition having 6 tools in the AIGER-based track. The 3rd Reactive Synthesis Competition (SYNTCOMP 2016): Benchmarks, Participants & Results