An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Paper

First seen 7/13/2026

Last seen 7/13/2026

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RELATIONSHIPS

39 connections

Fault Injection uses → 95% 2e

The paper uses fault injection to test detection capabilities.

Fault Injection Manager uses → 95% 2e

The paper uses the Fault Injection Manager to control fault injection experiments.

Fault Emulation Engine uses → 95% 2e

The paper uses the Fault Emulation Engine to collect fault data.

Emulation ROM Side Loading uses → 95% 2e

The paper uses Emulation ROM Side Loading to rapidly load binary executables for testing.

Fault Trigger Binary Executable introduces → 95% 2e

The paper introduces the Fault Trigger Binary Executable as a minimized set of instructions for fault detection.

Fault-Run-Cycle-Based FTBE introduces → 95% 2e

The paper introduces the Fault-Run-Cycle-Based FTBE as one of two methods for generating the binary executable.

Access-Control Extension mentions → 85% 2e

The paper mentions Access-Control Extension as a related fault detection method.

Potato RISC-V processor uses → 95% 2e

The paper uses the Potato RISC-V processor as the target microprocessor for experiments.

Advanced Encryption Standard uses → 95% 2e

The paper uses the AES algorithm as the cryptographic workload to evaluate fault detection.

scan chain uses → 90% 2e

The paper uses DFT scan chains for fault injection and counter access.

ATPG-Based FTBE introduces → 95% 2e

The paper introduces the ATPG-Based FTBE as the second method for generating the binary executable.

Wishbone bus uses → 90% 2e

The paper uses the Wishbone bus as the interconnect for the Potato SoC.

Periodic Built-In-Self-Test introduces → 95% 2e

The paper proposes a hardware Periodic Built-In-Self-Test methodology.

Automatic Test Pattern Generation uses → 95% 2e

The paper uses ATPG methodology to generate binary executables for fault detection.

counter-based node monitoring uses → 95% 2e

The paper uses counter-based node monitoring infrastructure for fault detection.

Fault-Run-Cycle-Based FTBE evaluates → 95% 2e

The paper evaluates the RCBE for fault coverage and latency performance.

ATPG-Based FTBE evaluates → 95% 2e

The paper evaluates the ATPG-Based FTBE for fault coverage and latency performance.

severe fault mentions → 95% 2e

The paper defines and focuses on severe faults that lead to information leakage.

Access-Control Extension ← compares with 85% 1e

The paper compares the overhead of its approach to the ACE technique.

Design for Testability uses → 85% 1e

The paper uses DFT infrastructure such as scan chains as part of its methodology.

RTL uses → 85% 1e

The paper modifies the Potato RTL as part of the ATPG-based FTBE generation process.

Synopsys Design Compiler uses → 90% 1e

The paper uses Synopsys Design Compiler for area overhead analysis of the counter circuit.

Jim Plusquellic authored by → 100% 1e

Jim Plusquellic is listed as an author of the paper.

Tom J. Mannos authored by → 100% 1e

Tom J. Mannos is listed as an author of the paper.

Brian Dziki authored by → 100% 1e

Brian Dziki is listed as an author of the paper.

fault propagation latency evaluates → 90% 1e

The paper evaluates fault propagation latency for leakage scenarios.

Xilinx UltraScale+ MPSoC ZCU102 uses → 95% 1e

The paper uses the Xilinx ZCU102 board as the emulation platform.

Yosys uses → 90% 1e

The paper uses Yosys for synthesis as part of the ATPG-based flow.

Fault (open-source DFT toolchain) uses → 90% 1e

The paper uses the Fault open-source DFT toolchain for ATPG vector generation.

PODEM uses → 90% 1e

The paper uses PODEM test pattern algorithm for generating ATPG vectors.

Idris O. Somoye authored by → 100% 1e

Idris O. Somoye is listed as an author of the paper.

RISC-V online assembler uses → 90% 1e

The paper uses the RISC-V online assembler to convert instructions into RV32I binaries.

SystemVerilog testbench uses → 90% 1e

The paper uses a SystemVerilog testbench to extract processor state at fault-triggered cycles.

ASAP7 standard cell library uses → 90% 1e

The paper uses the ASAP7 standard cell library for overhead synthesis.

osu035 standard cell library uses → 90% 1e

The paper uses the osu035 standard cell library for ATPG netlist synthesis.

Coremark benchmark evaluates → 85% 1e

The paper evaluates the Coremark benchmark as a comparison binary for fault coverage and latency.

Self-Assertion-Based Countermeasures evaluates → 85% 1e

The paper references evaluations of Self-Assertion-Based Countermeasures for fault detection comparison.

Dynamic Implementation Verification Architecture mentions → 85% 1e

The paper mentions DIVA as related work for fault detection.

FPGA Emulation uses → 90% 1e

The paper uses FPGA emulation for fault injection experiments.