Access-Control Extension

Access-Control Extension (ACE)

Concept

A specialized custom instruction set, coined 'Access-Control Extension' (ACE), introduced as part of a predominantly software-based fault detection scheme for RISC-V microprocessors. ACE interacts with a custom-instrumented full-scan chain to test the processor, and is used as a comparative baseline against counter-based periodic fault detection approaches.

First seen 7/13/2026

Last seen 7/13/2026

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Overview

Access-Control Extension (ACE) is a special custom instruction set, coined in the work of the authors cited as [8] in An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor. ACE forms the software component of a predominantly software-based fault detection scheme supplemented by hardware ^[1].

Design and Operation

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RELATIONSHIPS

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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor ← mentions 85% 2e

The paper mentions Access-Control Extension as a related fault detection method.

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor compares with → 85% 1e

The paper compares the overhead of its approach to the ACE technique.

LINKED ENTITIES

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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor MENTIONS Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] ACE is a special custom instruction set coined by the authors of [8] as part of a predominantly software-based fault detection scheme supplemented by hardware, interacting with a custom-instrumented full-scan chain to test the microprocessor. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[2] ACE instructions are privileged to only the ACE firmware, and the implementation is described as complicated. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[3] The specialized ACE instructions add complexity to the microprocessor, create a side-channel attack vector, and the tree architecture exposes no avenue to target information leakage sites. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[4] ACE requires 32 KBits of memory allocation with an area overhead of 18.7% on the Potato core (28,510 µm²); ACE Hybrid has the same 32 KBits memory but 5.8% area overhead. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[5] Performance overhead of the proposed Counter-Measure + FTBE methodology is estimated using a 100-million-instruction checkpoint interval akin to ACE, with a minimal number of scan clock cycles (120 using five 24-bit counters). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor