Advanced Encryption Standard

Concept

The Advanced Encryption Standard (AES) is a symmetric-key block cipher standardized by the U.S. National Institute of Standards and Technology (NIST), selected as the Rijndael algorithm. In the related fault-detection work, AES is used as the workload executed on the Potato RISC-V microprocessor to exercise the fault emulation platform and to identify information-leakage fault sites.

First seen 7/13/2026

Last seen 7/13/2026

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Overview

The Advanced Encryption Standard (AES) is a symmetric-key block cipher adopted as a Federal Information Processing Standard by the National Institute of Standards and Technology (NIST). AES was selected through an open competition and is based on the Rijndael algorithm. The standard defines operations over fixed-size blocks and supports multiple key sizes.

Polynomial and Algebraic Description

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RELATIONSHIPS

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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor ← uses 95% 2e

The paper uses the AES algorithm as the cryptographic workload to evaluate fault detection.

Fault-Run-Cycle-Based FTBE ← uses 90% 2e

The RCBE uses AES execution data to identify fault-triggered cycles.

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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor USES Extracted graph relationship

Fault-Run-Cycle-Based FTBE USES Extracted graph relationship

CITATIONS

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[1] AES is used as the executable binary loaded onto the Potato RISC-V microprocessor for fault-emulation experiments. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[2] The Fault Emulation Engine collects serial and address-bus data as Potato executes AES, combined with a binary search routine to determine fault-effect latency. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[3] Counter values for each node are generated in a fault-free run of the AES binary in increments of 1024 cycles from cycle 0 to cycle 6,717,440. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[4] BFTCs and IFTCs for the AES binary on Potato are tabulated for stuck-at-0, stuck-at-1, delay, and invert fault classes, with the highest-latency delay fault at cycle 6,078,464 (1024-cycle) and 6,076,072 (single-cycle). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[5] A SystemVerilog test bench simulates Potato to the IFTC under the AES binary and stores general-purpose register values, the previous 10 instructions, and memory/Wishbone bus accesses. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[6] Rijndael AES is described via polynomials, with particular attention to the structure of the S-Box. A Polynomial Description of the Rijndael Advanced Encryption Standard

[7] AES is used as the cipher behind full-disk encryption (FDE) for HDD security, with adjustable key sizes. An Adaptive Technique using Advanced Encryption Standard to Implement Hard Disk Security

[8] The cited RISC-V framework enables fast implementation and post-synthesis verification of cryptographic hardware accelerators for AES, but has not been shown to detect hardware-based information-leakage faults. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor