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STIMSMITH

Synopsys Design Compiler

Tool
First seen 7/5/2026
Last seen 8/3/2026
Evidence 10 chunks

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RELATIONSHIPS

6 connections
Hardware accelerated constrained random test generation ← uses 100% 2e
Synopsys Design Compiler is used for synthesizing the hardware circuits described in the paper.
FISH (Fast Instruction SyntHesis) ← uses 100% 2e
FISH uses Synopsys Design Compiler for hardware synthesis and estimation
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor ← uses 90% 1e
The paper uses Synopsys Design Compiler for area overhead analysis of the counter circuit.
Hardware Execution Latency Estimation ← uses 95% 1e
Hardware execution latency is estimated by Synopsys Design Compiler synthesis
Subgraph Selection ← uses 90% 1e
Subgraph selection uses actual Synopsys synthesis results
Cascade ← uses 100% 1e
CASCADE uses Synopsys Design Compiler for logic synthesis and library translation.