Hardware accelerated constrained random test generation
PaperFirst seen 7/7/2026
Last seen 7/7/2026
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44 connectionsThe paper presents a two-step approach for constrained random synthesis.
The paper uses constraint pre-processing in software as the first step of its methodology.
Entailed regions are pre-computed in software and used in hardware for random value selection.
The paper addresses and solves the problem of constrained random value selection in hardware.
The paper targets hardware accelerated simulation as its application context.
The paper applies its methodology to layered test bench architectures.
ILP is used during the software preprocessing phase to compute boundary points of the solution polygon.
LFSR is used as a pseudo-random generator in the hardware synthesis step.
Strip computation is a key step in the software preprocessing phase of the paper.
Overlapping constraint sets are computed per strip and used to refine bounds in hardware.
Strip weights are used to assign selection probabilities to strips proportional to the solution volume.
Bound refinement is used after each variable assignment to constrain remaining variables.
The paper targets systems of linear constraints where each constraint involves at most two variables.
The paper uses projection of multi-dimensional solution spaces onto 2D planes as part of its methodology.
The paper integrates its methodology with the Reference Verification Methodology layered architecture.
The paper integrates its methodology with the Verification Methodology layered architecture.
The paper reports results on ARM AMBA AHB bus protocol test bench architectures.
The paper reports results on IBM CoreConnect bus protocol test bench architectures.
ILOG CPLEX is used as the ILP solver to compute boundary points of the solution polygon.
Synopsys Design Compiler is used for synthesizing the hardware circuits described in the paper.
The paper presents constrained random test bench results for ARM AMBA bus protocol.
The paper presents constrained random test bench results for IBM CoreConnect bus protocol.
FPGAs are used as the hardware emulation platform in hardware accelerated simulation.
Bus Functional Models/Drivers are moved into hardware as part of the layered test bench methodology.
The paper is motivated by coverage-driven randomised verification as the modern verification paradigm.
The RefineBound procedure is introduced for refining variable bounds after each variable assignment.
The ReCompTotWt procedure is introduced for recomputing total strip weights after bound refinement.
B. Pal is listed as an author of the paper.
A. Sinha is listed as an author of the paper.
P. Dasgupta is listed as an author of the paper.
P.P. Chakrabarti is listed as an author of the paper.
K. De is listed as an author of the paper.
The GenerateSolution algorithm is the overall synthesis algorithm combining all hardware blocks.
The ComputeStrip algorithm is introduced for decomposing the convex polygon into strips.
PCI Bus is mentioned as one of the standard bus protocols for which verification IPs were modeled.
Pseudo-random number generation via LFSR is used in the hardware random value selection step.
Constraint backtracking search is mentioned as a state-of-the-art technique used by software solvers.
The design-under-test is the component being verified in the hardware accelerated simulation framework.
SystemVerilog is mentioned as a design and verification language that supports constrained random test benches.
OpenVera is mentioned as a hardware verification language supporting constrained random verification.
Specman-Elite is mentioned as a hardware verification language supporting constrained random verification.
The GenRandNum procedure is introduced and described as a hardware block for random number generation within bounds.
The paper splits inequality constraints into two disjoint conjunctive constraint sets.
The convex polygon encapsulating the solution region is computed during software preprocessing.