Constrained Random Value Selection

Concept

Constrained random value selection is the problem of synthesising a hardware circuit that deterministically generates pseudo-random valuations of variables subject to a known set of constraints. It is a key component of hardware-accelerated constrained random test generation, where software pre-processing decomposes the constraint solution space and a hardware generator (typically LFSR-based) emits valuations only from within the entailed solution regions.

First seen 7/7/2026

Last seen 7/7/2026

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Constrained Random Value Selection

Problem Statement

Given a set of variables and a set of constraints over these variables, the goal is to synthesise a circuit in hardware that deterministically generates pseudo-random valuations of these variables subject to the given constraints. The aim is to develop a tool that performs this synthesis from a given system of constraints.

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Hardware accelerated constrained random test generation ← uses 100% 2e

The paper addresses and solves the problem of constrained random value selection in hardware.

two-step constrained random synthesis ← uses 100% 1e

The two-step methodology performs constrained random value selection in hardware as the second step.

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Hardware accelerated constrained random test generation USES Extracted graph relationship

two-step constrained random synthesis USES Extracted graph relationship

CITATIONS

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[1] Constrained random value selection in hardware is the central focus of hardware-accelerated constrained random test generation: given a set of variables and constraints, synthesise a circuit that deterministically generates pseudo-random valuations satisfying the constraints. Hardware accelerated constrained random test

[2] The generated circuit must guarantee that all valuations satisfying the constraints have a non-zero probability of being selected. Hardware accelerated constrained random test

[3] Constraints used in verification test benches are typically simple: range constraints on individual variables and two-variable constraints (one variable constrained relative to another); constraints involving more than two variables are rare in AMBA, IBMCC, and PCI Bus test benches. Hardware accelerated constrained random test

[4] Step 1 of the methodology uses an integer linear programming (ILP) solver in software to deduce a set of regions covering the constraint-satisfying valuations; this pre-processing is executed only once before emulation. Hardware accelerated constrained random test

[5] Step 2 of the methodology synthesises a hardware constrained random test generator using a pseudo-random generator based on a linear feedback shift register (LFSR) together with constraint-specific circuitry that restricts the generator to the regions entailed by step 1. Hardware accelerated constrained random test

[6] The main challenge is that the entailed regions produced by the software step must be consumable by the hardware step efficiently in terms of clock cycles per random valuation and area overhead of the generating circuit. Hardware accelerated constrained random test