ARM AMBA AHB

Concept

ARM AMBA AHB (Advanced High-performance Bus) is an on-chip bus protocol from ARM's AMBA family that is used in the synthesis experiments of a paper on hardware-accelerated constrained-random test generation. The paper exercises AHB designs (Arbiter, Master, Slave) as DUTs, uses the AMBA Specification Rev 2.0 as a reference, and analyzes constraint-synthesis complexity for typical AHB transaction scenarios (Split/Retry responses, half-word reads, byte-lane selection, burst transfers).

First seen 7/7/2026

Last seen 7/7/2026

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ARM AMBA AHB

Overview

ARM AMBA AHB (Advanced High-performance Bus) is part of ARM's AMBA (Advanced Microcontroller Bus Architecture) family of on-chip interconnect protocols. In the context of verification research, it serves as one of the industry-standard on-chip bus protocols used to evaluate hardware-accelerated constrained-random test generation.

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Hardware accelerated constrained random test generation ← evaluates 100% 2e

The paper reports results on ARM AMBA AHB bus protocol test bench architectures.

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Hardware accelerated constrained random test generation EVALUATES Extracted graph relationship

CITATIONS

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[1] AMBA AHB is an industry-standard on-chip bus protocol used as a target for hardware-accelerated constrained-random test generation synthesis experiments. Hardware accelerated constrained random test

[2] The paper evaluates AHB Arbiter, AHB Master, and AHB Slave DUT components with associated environment constraints. Hardware accelerated constrained random test

[3] An example AHB constraint scenario uses 6 variables (addr:32, burst:3, fracad:2, size:3, trans:2, resp:2) yielding 15 planes and 11 input constraints. Hardware accelerated constrained random test

[4] The AMBA Specification Rev 2.0 is the canonical reference for the AHB protocol. Hardware accelerated constrained random test

[5] The AHB on-chip bus protocol test benches use constraints involving either ranges of individual variables or linear constraints involving two variables. Hardware accelerated constrained random test

[6] The research on hardware-accelerated constrained-random test generation was supported by Synopsys (India) Pvt. Ltd. and DST, Government of India. Hardware accelerated constrained random test

[7] Design Compiler from Synopsys was used to synthesize the hardware generated for AHB constraint scenarios. Hardware accelerated constrained random test