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Bi-variate Linear Constraints

Concept

Bi-variate linear constraints are linear constraints that involve exactly two variables at a time. In the context of hardware-accelerated constrained random test generation, systems consisting solely of such bi-variate constraints (together with single-variable range constraints) have been shown to be relevant and often adequate for modeling the environment of on-chip bus protocols such as IBM CoreConnect and AMBA AHB. Their tractable structure enables efficient geometric decomposition (into planes and strips) and the synthesis of modest-area hardware generators that emit random satisfying valuations within a few clock cycles. Synthesis of more general constraints involving an arbitrary number of variables remains an open problem.

First seen 7/7/2026
Last seen 7/7/2026
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Bi-variate Linear Constraints

Definition

A bi-variate linear constraint is a linear constraint (an inequality or equation) whose coefficients reference exactly two variables. In the test-generation literature, systems that mix bi-variate linear constraints with single-variable range constraints arise frequently when describing the environment of a design under test (DUT).

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RELATIONSHIPS

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The paper targets systems of linear constraints where each constraint involves at most two variables.
two-step constrained random synthesis ← uses 100% 1e
The methodology targets bi-variate linear constraints where each constraint involves at most two variables.

CITATIONS

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6 citations — click to expand
[1] Systems of constraints involving only bi-variate constraints are both relevant and often adequate in practice for modeling on-chip bus verification environments. Hardware accelerated constrained random test
[2] On-chip bus test-bench constraints generally consist of ranges over individual variables or linear constraints involving two variables. Hardware accelerated constrained random test
[3] A six-variable AHB Master constraint with widths (32,3,3,2,2,2) yields 15 planes via the C(6,2) decomposition and uses 11 input constraints. Hardware accelerated constrained random test
[4] Synthesized circuits for bi-variate constraint systems have modest area overhead and produce random satisfying valuations within a few clock cycles. Hardware accelerated constrained random test
[5] Synthesis of general constraints involving any number of variables (beyond the bi-variate plus univariate-range case) remains an open problem. Hardware accelerated constrained random test
[6] The bi-variate structure enables a plane/strip decomposition: each pair of variables forms a plane and each bi-variate constraint is realized as a strip within that plane, with the number of planes equal to C(n,2). Hardware accelerated constrained random test