ASAP7 standard cell library

Concept

A predictive 7nm standard cell library used with Synopsys Design Compiler for area estimation of synthesized digital circuits, notably the counter-based counter-measure hardware in the cited RISC-V fault-detection study.

First seen 7/13/2026

Last seen 7/13/2026

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Overview

The ASAP7 standard cell library is a predictive Process Design Kit (PDK) targeting a 7nm FinFET technology node. It provides standard cells used by commercial synthesis tools to estimate area, timing, and power of digital designs. In the cited study, ASAP7 is used in conjunction with Synopsys Design Compiler to synthesize the counter circuit of a counter-based Counter-Measure (CM) for periodic information-leakage fault detection on a RISC-V microprocessor.

Role in the Cited Work

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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor ← uses 90% 1e

The paper uses the ASAP7 standard cell library for overhead synthesis.

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An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor USES Extracted graph relationship

CITATIONS

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[1] The counter circuit was analyzed for area overhead using Synopsys Design Compiler and the ASAP7 standard cell library, yielding 339 µm² per counter. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[2] Five counters deployed give an area overhead of 1695 µm², versus the Potato core area of 28,510 µm² (≈5.9% fractional overhead). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[3] Compared against the Rocket core area of 112,224 µm², overhead is 2.9% (RCBE) and 2.2% (ATPGB). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor