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ASAP7 standard cell library

Concept WIKI v1 · 7/13/2026

A predictive 7nm standard cell library used with Synopsys Design Compiler for area estimation of synthesized digital circuits, notably the counter-based counter-measure hardware in the cited RISC-V fault-detection study.

Overview

The ASAP7 standard cell library is a predictive Process Design Kit (PDK) targeting a 7nm FinFET technology node. It provides standard cells used by commercial synthesis tools to estimate area, timing, and power of digital designs. In the cited study, ASAP7 is used in conjunction with Synopsys Design Compiler to synthesize the counter circuit of a counter-based Counter-Measure (CM) for periodic information-leakage fault detection on a RISC-V microprocessor.

Role in the Cited Work

The cited paper, An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor, uses ASAP7 to quantify the area overhead of the proposed hardware counter mechanism:

  • The counter circuit consists of two 24-bit counters.
  • Synthesis with Synopsys Design Compiler and ASAP7 yields an area of 339 µm² per counter.
  • Deploying five counters results in an area overhead of 1695 µm².
  • Compared with the Potato core area of 28,510 µm², the fractional area overhead is approximately 5.9%.
  • Using the larger Rocket core area of 112,224 µm², the overhead falls to about 2.9% (RCBE) and 2.2% (ATPGB).

These results indicate that ASAP7-based synthesis provides concrete area figures that support claims of low hardware overhead for the counter-based detection technique relative to the host processor.

Significance

  • Predictive 7nm modeling: Enables research-grade area estimation without requiring access to a foundry 7nm PDK.
  • Tool integration: Pairs with commercial synthesis (Synopsys Design Compiler) for reproducible area numbers.
  • Overhead benchmarking: Provides the baseline numbers used in the cited paper's overhead analysis table comparing RCBE, ATPGB, ACE, and ACE Hybrid counter-measures.

Related Entities

  • Paper (incoming): An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor — uses ASAP7 for area synthesis of the counter-based CM.

LINKED ENTITIES

1 links
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor USES

CITATIONS

3 sources
3 citations
[1] The counter circuit was analyzed for area overhead using Synopsys Design Compiler and the ASAP7 standard cell library, yielding 339 µm² per counter. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
[2] Five counters deployed give an area overhead of 1695 µm², versus the Potato core area of 28,510 µm² (≈5.9% fractional overhead). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
[3] Compared against the Rocket core area of 112,224 µm², overhead is 2.9% (RCBE) and 2.2% (ATPGB). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor