Coremark benchmark

Concept

CoreMark is referenced in the supplied evidence as a benchmark used in embedded and processor-evaluation contexts, including RISC-V CPU-core verification work and bare-metal firmware instrumentation research.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

The Coremark benchmark is treated in the available evidence as a benchmark workload for embedded and processor-oriented evaluation. In the supplied RISC-V verification thesis, Coremark appears as a subsection under an experimental-evaluation chapter's "Benchmarks" section, alongside Dhrystone. The provided public arXiv context also identifies "CoreMark benchmark" as one of the real-world targets used to evaluate PIFER, a static binary-instrumentation framework for bare-metal embedded firmware.

Use in evaluation workflows

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LINKED ENTITIES

2 links

UVM Based Design Verification of a RISC-V CPU Core EVALUATES Extracted graph relationship

Benchmarks PART_OF Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] Coremark appears in the RISC-V CPU-core verification thesis as part of Chapter 5, 'Experimental evaluation,' under Section 5.3, 'Benchmarks.' [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The PIFER paper's public arXiv summary identifies the CoreMark benchmark as one of the real-world, complex firmware targets used in its evaluation. Abusing Processor Exception for General Binary Instrumentation on Bare-metal Embedded Devices

[3] The PIFER public arXiv summary reports that PIFER correctly instrumented 98.9% of instructions. Abusing Processor Exception for General Binary Instrumentation on Bare-metal Embedded Devices