Overview

The Coremark benchmark is treated in the available evidence as a benchmark workload for embedded and processor-oriented evaluation. In the supplied RISC-V verification thesis, Coremark appears as a subsection under an experimental-evaluation chapter's "Benchmarks" section, alongside Dhrystone. The provided public arXiv context also identifies "CoreMark benchmark" as one of the real-world targets used to evaluate PIFER, a static binary-instrumentation framework for bare-metal embedded firmware.

Use in evaluation workflows

RISC-V CPU-core verification

In UVM based design verification of a RISC-V CPU core, the table of contents places "Coremark" under Chapter 5, "Experimental evaluation," specifically within Section 5.3, "Benchmarks." This supports its role as one of the benchmark-based evaluation items in that work.

Bare-metal embedded firmware instrumentation

The arXiv summary for Abusing Processor Exception for General Binary Instrumentation on Bare-metal Embedded Devices states that PIFER was evaluated against real-world, complex firmware including Zephyr RTOS, the CoreMark benchmark, and a closed-source commercial product. The same summary reports that PIFER correctly instrumented 98.9% of instructions in its evaluation.

Scope of supported claims

The provided evidence supports CoreMark's use as a benchmark in the above evaluation contexts. It does not provide enough detail to describe CoreMark's internal workload composition, scoring formula, official maintainers, benchmark rules, or comparative performance metrics.