μARCHIFI

Tool

First seen 7/6/2026

Last seen 7/6/2026

Evidence 12 chunks

NEIGHBORHOOD

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RELATIONSHIPS

26 connections

FaultRTLIL ← part of 100% 2e

FaultRTLIL is a translation pass that is part of the μARCHIFI tool.

Ibex evaluates → 100% 2e

μARCHIFI is evaluated using the Ibex RISC-V processor.

RISC-V uses → 100% 2e

μARCHIFI is demonstrated on RISC-V use cases.

Verilog uses → 100% 2e

μARCHIFI takes as input a processor hardware description in Verilog.

Binary Program uses → 100% 2e

μARCHIFI takes a binary software program as input.

Hardware Transition System uses → 100% 2e

μARCHIFI models the hardware processor as a transition system.

PONO compares with → 90% 2e

μARCHIFI is evaluated with PONO as one of the model checkers.

BTORMC compares with → 90% 2e

μARCHIFI is evaluated with BTORMC as one of the model checkers.

Yosys uses → 100% 2e

μARCHIFI is implemented using and integrated into the Yosys toolchain.

Faulty Transition System implements → 100% 2e

μARCHIFI generates and implements the faulty transition system model.

Microarchitectural Fault Model implements → 100% 2e

μARCHIFI implements microarchitectural fault models including combinational and sequential faults.

Attacker Model implements → 100% 2e

μARCHIFI integrates an attacker model into the formal system.

bounded model checking uses → 100% 2e

μARCHIFI uses bounded model checking for verification.

Sandboxing uses → 100% 2e

μARCHIFI supports sandboxing as a verification strategy.

Concretization uses → 100% 2e

μARCHIFI uses concretization to split verification into sub-problems.

Reachability Property uses → 100% 2e

μARCHIFI frames the verification problem as a reachability property check.

program counter uses → 95% 2e

μARCHIFI uses the program counter to distinguish execution paths in sandboxing and concretization.

VerifyPIN evaluates → 100% 2e

μARCHIFI is evaluated on the VerifyPIN use cases.

AES Key Schedule evaluates → 100% 2e

μARCHIFI is evaluated on the AES key schedule use case.

μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections ← introduces 100% 1e

The paper introduces μARCHIFI as a new open-source tool for formal modeling and verification of microarchitectural fault injections.

RTL uses → 100% 1e

μARCHIFI automatically implements the fault model from the hardware design description at the RTL level.

RTLIL uses → 100% 1e

μARCHIFI works on the RTLIL intermediate representation of Yosys.

CV32E40P evaluates → 100% 1e

μARCHIFI is evaluated using the CV32E40P RISC-V processor.

SW/HW Co-verification uses → 100% 1e

μARCHIFI supports SW/HW co-verification by combining hardware and software models.

VCD Waveform Trace uses → 90% 1e

μARCHIFI produces VCD waveform traces as output from model-checker results.

SystemVerilog Assertion uses → 95% 1e

μARCHIFI supports SystemVerilog Assertions to specify the attacker's goal.