Binary Program

Concept

A binary program is a software artifact expressed in compiled, machine-readable form as a sequence of instructions for a target instruction set architecture (ISA). Binary programs are central objects of analysis in microarchitectural fault-injection verification (e.g., the µARCHIFI workflow), as engineered stimuli for Periodic Built-In-Self-Test (PBIST) of microprocessors (FTBE), in machine-learning–based detection of cryptographic primitives, and in binary similarity analysis.

First seen 7/6/2026

Last seen 7/13/2026

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Binary Program

Definition

A binary program is a software program in its compiled, machine-code representation, consisting of processor instructions targeted at a specific instruction set architecture (ISA). In the µARCHIFI workflow, a binary program is one of the three primary inputs supplied alongside a hardware description (in Verilog) and an attacker model specifying the fault model [chunk: cc0353b3; chunk: e2d812bc]. The program must be compiled for the corresponding ISA of the processor under analysis so that its machine instructions can be symbolically interpreted against the hardware transition system [chunk: cc0353b3].

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RELATIONSHIPS

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μARCHIFI ← uses 100% 2e

μARCHIFI takes a binary software program as input.

LINKED ENTITIES

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Automatic Test Pattern Generation (ATPG) related_concept ATPG tools are used in one of the two reported methods (ATPGB) to coerce test vectors into a coherent low-instruction binary program.

CITATIONS

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[1] In the µARCHIFI workflow, a binary program is one of three primary inputs alongside a Verilog hardware description and an attacker model specifying the fault model, and must be compiled for the corresponding ISA. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections

[2] µARCHIFI uses bounded model checking to verify reachability of an attacker goal φ given the hardware design, the binary program, and the attacker model. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections

[3] µARCHIFI use cases include VerifyPIN (compiled with -Og and -Os) on CV32E40P and Secure Ibex cores, and KeySchedule (AES) compiled with -Os on the Ibex core. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections

[4] Verification tractability in µARCHIFI requires a trade-off between the size of the hardware design, the size of the analyzed program, and the complexity of the fault model. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections

[5] A Fault Trigger Binary Executable (FTBE) is a minimized set of instructions designed to recreate a processor state that leads to information leakage in the presence of a fault with minimal latency. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[6] Two FTBE generation methods are described: Run-Cycle-Based (RCBE), which uses counter-based run-cycle analysis to recreate processor state, and ATPG-Based (ATPGB), which coerces ATPG test vectors into coherent processor instructions and register-file values. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[7] Minimizing binary size (e.g., to less than 100 instructions) is an important design goal because the FTBE will be stored in on-chip memory for periodic fault detection. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[8] The default AES binary execution on the Potato RISC-V SoC spans 6,717,440 clock cycles, providing the baseline for FTBE latency comparison. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[9] RCBE produces three binaries B0, B1, B2 from IFTCs 6,076,072, 1,728,512, and 550,800 respectively, triggering 9, 113, and 122 SevereFaults; ATPGB detects 188 SevereFaults with fewer instructions; Coremarks triggers 191 SevereFaults; hello world triggers only 1. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[10] The RCBE detects all SevereFaults within 4096 run clock cycles and the ATPGB triggers 188 faults by the 4096-cycle index, far outperforming standard binaries where severe faults can have latencies up to 6 million cycles. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[11] The PCAP interface configures the FPGA with the instrumented Potato bitstream, and a Wishbone side-load (ERSE) overrides boot memory with the executable binary under test. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[12] Combining multiple RCBEs into one binary is achieved by overwriting registers that differ between binaries and updating the corresponding instructions. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[13] PEM represents binary program semantics via a probabilistic execution engine that samples both the input space and the program-path space, achieving 96% precision on 9 real-world projects spanning 35k functions. PEM: Representing Binary Program Semantics for Similarity Analysis via a Probabilistic Execution Model

[14] Machine-learning approaches can detect and identify cryptographic primitives in small single-purpose compiled binary programs, motivating automated malware triage. Automated detection and classification of cryptographic algorithms in binary programs through machine learning