Automatic Test Pattern Generation (ATPG)

Concept

Automatic Test Pattern Generation (ATPG) is an electronic design automation (EDA) process that algorithmically generates input stimulus vectors (test patterns) used to detect structural faults in digital and integrated circuits. ATPG is foundational to manufacturing test and is closely coupled with Design-for-Test (DfT) structures such as scan chains. It is applied to classical fault models including stuck-at and transition faults, and supports dependability analysis and test plan development in safety-critical and embedded systems. Recent research extends ATPG with machine learning techniques, including reinforcement learning (RL) and graph neural networks (GNNs), to address scalability and runtime challenges of traditional algorithms.

First seen 6/6/2026

Last seen 6/6/2026

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WIKI

Overview

Automatic Test Pattern Generation (ATPG) is an electronic design automation (EDA) process responsible for efficiently generating test patterns used to exercise digital circuits and detect manufacturing defects or in-field faults. ATPG algorithms take as input a circuit netlist, a target fault model, and constraints, and produce a set of input vectors that excite each modeled fault and propagate its effect to an observable point.

Role in IC Design and Testing

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RELATIONSHIPS

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Scan-Based DfT with ATPG ← uses 95% 2e

Scan-based DfT supports ATPG for structural faults.

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Scan-Based DfT with ATPG USES Extracted graph relationship

CITATIONS

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[1] ATPG is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns, and traditional ATPG struggles with long execution times to achieve expected fault coverage, impacting time-to-market. InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

[2] Recent machine-learning ATPG approaches use reinforcement learning (RL) and graph neural networks (GNNs) and face issues of reward delay in RL and inadequate circuit representation in GNN-based methods. InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

[3] The InF-ATPG framework partitions circuits into fanout-free regions (FFRs) and incorporates ATPG-specific features into a QGNN architecture to guide RL, reducing backtracks by 55.06% on average vs traditional ATPG and 38.31% vs prior ML ATPG approaches, while improving fault coverage. InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

[4] Identification of safe faults in electronic systems is crucial for dependability analysis and test plan development, is poorly supported by available EDA tools, and is addressed by applying ATPG techniques to embedded systems (e.g., the OpenRisc1200 processor). New categories of Safe Faults in a processor-based Embedded System

[5] Scan-based DfT remains relevant for RISC-V cores, enabling sequential element controllability and observability during test shifts, which supports ATPG for structural faults such as stuck-at and transition faults. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...

[6] Scan/BIST is listed as a Design-for-Test architecture with scan-chain DfT supported by ATPG. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...