Program Counter
ConceptA program counter is part of a processor's architectural state. In the VAMP ISA model, it is represented as pcp, a 30-bit register holding the address of the next instruction to be executed and used with a delayed program-counter mechanism.
First seen 5/26/2026
Last seen 7/16/2026
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Definition
A program counter is a processor state element used to identify the instruction address involved in execution. In architectural-style processor models, the architectural state is commonly represented as a record combining state components such as a register file, status flags, and a program counter. [C1]
VAMP processor model
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12 connectionsThe program counter is one of the registers described by register models.
μARCHIFI uses the program counter to distinguish execution paths in sandboxing and concretization.
The program counter (PC) is part of the architectural state visible at the ISA level.
Each template includes an equation for the effect on the program counter.
Software interrupts alter the program counter to redirect execution.
Hardware initialization sets the program counter to a predetermined entry point.
Triple Modular Redundancy is suggested to protect the program counter from SEUs.
VAMP includes a program counter register.
The program counter is a register in the Ibex Core identified as highly vulnerable.
Sandboxing uses the program counter to constrain execution paths.
Concretization uses the program counter to enumerate different execution paths.
Execution of the ADDC instruction affects the program counter.
LINKED ENTITIES
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[1] C1: Architectural-style processor models commonly include a program counter as part of the architectural state alongside components such as a register file and status flags. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] C2: In the VAMP ISA configuration, pcp is a 30-bit program-counter register containing the address of the next instruction to be executed, and it supports the delayed-pc mechanism. Test Program Generation for a Microprocessor: A Case Study
[3] C3: The VAMP ISA configuration includes dcp as a delayed program counter that remains unchanged while the next instruction is fetched through pcp until the current instruction completes. Test Program Generation for a Microprocessor: A Case Study
[4] C4: The VAMP ISA configuration is composed of the program counter, delayed program counter, general-purpose registers, special-purpose registers, and memory model. Test Program Generation for a Microprocessor: A Case Study
[5] C5: Architectural-style modeling explicitly identifies architectural state and defines a next_state macro capturing effects of instructions and interrupts on that state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[6] C6: In the VAMP assembler abstraction, pcp is a natural number representing the program counter and dcp is a natural number representing the delayed program counter. Test Program Generation for a Microprocessor: A Case Study
[7] C7: FPGA research compares conventional radix-2 program counters with feedback-shift-register program counters, reporting constant-time bit-width scaling for FSR counters and proposing hybrid counters for cache-coherency concerns. Cyclic Sequence Generators as Program Counters for High-Speed FPGA-based Processors