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VAMP (Verified Architecture Microprocessor)

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VAMP is a verified, pipelined RISC microprocessor developed in the Verisoft and VerisoftXT research context. It is modeled in Isabelle/HOL, exposes an assembly-level instruction-set model called VAMPasm, and has been used as a case study for model-based conformance-test generation with HOL-TestGen.

First seen 5/26/2026
Last seen 5/26/2026
Evidence 4 chunks
Wiki v1

WIKI

Overview

VAMP (Verified Architecture Microprocessor) is a realistic RISC processor model inspired by IBM's G5 architecture. It was developed and verified in the German Verisoft and VerisoftXT research projects, whose verification goal covered computer systems from application-level software down to silicon-level hardware design. [VAMP origin and verification context]

Within the Verisoft architecture, work on VAMP focuses on the hardware layer, especially the assembly-level instruction-set model known as VAMPasm. The processor is described as a pipelined reduced instruction set computer based on out-of-order execution. [VAMPasm and microarchitecture summary]

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NEIGHBORHOOD

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RELATIONSHIPS

13 connections
VAMP ISA implements → 100% 2e
VAMP implements the VAMP ISA at the assembly level.
Instruction Set Architecture ← part of 100% 2e
The VAMP has a formal ISA model.
Test Program Generation for a Microprocessor: A Case-Study ← evaluates 90% 2e
The paper evaluates the VAMP processor's conformance to its formal model.
Verisoft project part of → 100% 1e
VAMP was developed as part of the Verisoft project.
VerisoftXT project part of → 100% 1e
VAMP was also developed in the context of the VerisoftXT project.
pipelined processor implements → 100% 1e
VAMP is a pipelined processor.
memory management unit ← part of 100% 1e
The VAMP includes two Memory Management Units.
general purpose registers ← part of 100% 1e
VAMP includes a set of 32 general purpose registers.
special purpose registers ← part of 100% 1e
VAMP includes a set of special purpose registers.
program counter ← part of 100% 1e
VAMP includes a program counter register.
out-of-order execution implements → 100% 1e
VAMP is based on the out-of-order execution principle.
DLX instruction set implements → 100% 1e
The VAMP implements the full DLX instruction set.
IBM G5 architecture derived from → 90% 1e
VAMP is inspired by IBM's G5 architecture.

LINKED ENTITIES

2 links
Isabelle/HOL specified_using The evidence states that a formal model of the VAMP processor was developed in Isabelle/HOL and that an Isabelle/HOL specification of the programmer's model was introduced.
HOL-TestGen used_for_test_generation The evidence states that HOL-TestGen is used to generate test sequences from the VAMP model.

CITATIONS

6 sources
6 citations — click to expand
[1] VAMP origin and verification context Test Program Generation for a Microprocessor: A Case Study
[2] VAMPasm and microarchitecture summary Test Program Generation for a Microprocessor: A Case Study
[3] ISA configuration elements and memory interface Test Program Generation for a Microprocessor: A Case Study
[4] Instruction set and assembler abstraction Test Program Generation for a Microprocessor: A Case Study
[5] Model-based conformance testing with HOL-TestGen Test Program Generation for a Microprocessor: A Case Study
[6] Testing scenarios and conformance relation Test Program Generation for a Microprocessor: A Case Study