Pipelined Processor

Concept

A pipelined processor is discussed in the evidence as a processor whose implementation state can reflect several instructions being processed concurrently in the pipeline. This complicates the mapping between low-level implementation registers and the programmer-visible architectural state, so verification and simulation approaches often use architectural abstractions, mapping functions, and next-state descriptions to hide pipeline details such as forwarding logic while preserving instruction-level behavior.

First seen 5/26/2026

Last seen 6/5/2026

Evidence 11 chunks

Wiki v2

WIKI

Pipelined Processor

A pipelined processor is a processor implementation in which the behavior of implementation registers can depend on several instructions that are currently being processed by the pipeline. In the cited verification work, this is presented as a reason why the implementation state of a pipelined design is more complex than the programmer-visible architectural state.^[1]

Architectural state and mapping functions

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RELATIONSHIPS

9 connections

Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← mentions 100% 3e

The paper uses a pipelined processor as the evaluation target for ISS generation.

Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← uses 90% 2e

Pipelined processors are the evaluation targets in the paper's experiments.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← evaluates 100% 1e

The case study uses a 32-bit pipelined RISC-V core as the DUT.

Processor Pipeline Forwarding Logic ← part of 100% 1e

Processor pipeline forwarding logic is part of the pipelined processor implementation.

MINRES The Good Core (TGC) part of → 90% 1e

The MINRES TGC is a 32-bit pipelined RISC-V processor.

MINRES The Good Core (TGC) ← implements 100% 1e

The MINRES TGC is a pipelined processor.

VAMP (Verified Architecture Microprocessor) ← implements 100% 1e

VAMP is a pipelined processor.

Branch Prediction ← part of 85% 1e

Branch prediction is a micro-architectural feature of pipelined processors that verification must handle.

Mapping Function uses → 95% 1e

Pipelined processors require mapping functions to abstract the pipeline implementation into an architectural view.

LINKED ENTITIES

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite MENTIONS Extracted graph relationship

Processor Pipeline Forwarding Logic PART_OF Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Pipeline implementation state and forwarding logic Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] Operation properties and architectural state Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] ISS motivation and design divergence risk Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] Architectural-style ISS generation Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] Pipeline effects in generated ISS performance Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] Small 5-stage pipelined processor experiment Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] Industrial 7-stage pipelined processor experiment Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[8] RCPN modeling of pipelined processors Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

[9] Controller synthesis for a two-stage pipelined processor Synthesizing Multiple Boolean Functions using Interpolation on a Single Proof