Mapping Function

Concept

A mapping function is an abstraction mechanism used in processor verification to relate an implementation state, such as RTL CPU state, to an architectural or ISA-level state. In the cited ISS-generation workflow, mapping functions such as vstate and vreg support equivalence proofs, while automatic instruction set simulator generation can proceed without first identifying them.

First seen 5/26/2026

Last seen 5/29/2026

Evidence 3 chunks

Wiki v1

WIKI

Definition

In the provided processor-verification context, a mapping function is an abstraction function used to describe the design-under-verification state in terms of a higher-level architectural state. This architectural state corresponds to the programmer-visible view of the processor, such as visible registers, rather than the detailed implementation registers. [C1]

Role in abstraction

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

5 connections

Architectural State ← uses 100% 2e

Mapping functions link the implementation state to the architectural state of the processor.

Architectural Style Properties part of → 100% 2e

Mapping functions are used in architectural style properties to link implementation state to architectural state.

Operation Properties part of → 90% 1e

Mapping functions are used in operation properties to relate implementation state to architectural state.

pipelined processor ← uses 95% 1e

Pipelined processors require mapping functions to abstract the pipeline implementation into an architectural view.

Operation Property ← uses 100% 1e

Operation properties use mapping functions to represent the architectural state of the design.

LINKED ENTITIES

2 links

Architectural State abstracts_to The evidence states that the DUV state is described in terms of a high-level or architectural state and that this abstraction is achieved by mapping functions.

Instruction Set Simulator not_required_for_generation The evidence states that mapping functions are not needed to automatically generate the ISS and that ISS generation can proceed without identifying mapping functions.

CITATIONS

6 sources

6 citations — click to expand

[1] Mapping functions abstract DUV state into high-level architectural state corresponding to the programmer-visible processor view. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] The mapping function vreg represents the architectural register file and hides or captures forwarding logic in a pipelined processor. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The abstraction function vstate maps the implementation state of the CPU to the ISA state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] The equivalence proof compares applying the CPU transition relation and then mapping to architectural state with applying the ISA next_state function. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] Finding appropriate mapping functions for architectural state is a sophisticated verification task, but those mapping functions are not needed to automatically generate the ISS. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] ISS generation does not require a full ISA-to-RTL equivalence proof upfront or prior identification of mapping functions between architectural state and implementation state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite