Operation Property

Concept

An operation property is a high-level verification property that describes the effect of one operation, such as a processor instruction, on a design's internal architectural state and output behavior. In processor verification, operation properties use architectural-state abstractions and mapping functions to express behavior compactly instead of reimplementing circuit logic.

First seen 5/29/2026

Last seen 5/29/2026

Evidence 2 chunks

Wiki v1

WIKI

Definition

An operation property is a verification property written from a high-level operation view of a design under verification. For a processor, an operation naturally corresponds to executing a single instruction. Each operation property describes how the design's internal state changes and how its output signals behave when that operation is executed. [C1]

Role in processor verification

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RELATIONSHIPS

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Complete Property Suite ← uses 90% 2e

The complete property suite consists of operation properties describing each instruction.

Mapping Function uses → 100% 1e

Operation properties use mapping functions to represent the architectural state of the design.

Architectural State uses → 100% 1e

Operation properties describe changes to the architectural state when instructions execute.

LINKED ENTITIES

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Complete Property Suite USES Extracted graph relationship

Architectural State USES Extracted graph relationship

Mapping Function USES Extracted graph relationship

CITATIONS

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7 citations — click to expand

[1] C1: An operation property expresses a high-level operation view; for processors, an operation corresponds to a single instruction, and each property describes internal-state changes and output-signal behavior during that instruction. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] C2: Operation properties are written compactly using abstraction techniques rather than by reimplementing complex circuit logic, and they describe the DUV state using high-level architectural state corresponding to programmer-visible registers. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] C3: Mapping functions link architectural state to implementation state and can capture pipeline forwarding logic in a compact form. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] C4: Completeness requirements can require an operation property to specify unchanged registers and output behavior; the ADD example proves the correct register-file update one time step later while hiding forwarding logic in the mapping function. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] C5: For ISS generation, the architecture description in a set of operation properties is implicit, so the cited work reformulates properties into an architectural style with explicit architectural state, interface behavior, next_state, and reset state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] C6: The architectural-style result uses a next_state function to capture the behavior of the verified design and serves as a formally checkable ISA description for C++ instruction set simulator generation. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] C7: Reformulating operation properties into architectural style does not require new detailed consideration of design behavior; identifying architectural-state components and instruction semantics is already part of verification, and mapping functions are not needed for automatic ISS generation. Generating an Efficient Instruction Set Simulator from a Complete Property Suite