Definition
An operation property is a verification property written from a high-level operation view of a design under verification. For a processor, an operation naturally corresponds to executing a single instruction. Each operation property describes how the design's internal state changes and how its output signals behave when that operation is executed. [C1]
Role in processor verification
Operation properties avoid directly reimplementing complex circuit logic in the verification language. Instead, they express the design's behavior in a compact, readable form using abstraction techniques. In the cited processor-verification setting, the design state is described as a high-level or architectural state, corresponding to the programmer-visible view of registers and related state. [C2]
This abstraction is achieved through mapping functions. For example, in a pipelined processor, the behavior of implementation registers can depend on multiple instructions currently in the pipeline. A mapping function can relate the architectural register file to the implementation and can capture forwarding logic, while remaining more compact than the implementation itself. [C3]
Contents of an operation property
An operation property typically specifies:
- the operation or instruction being considered;
- the architectural-state update caused by that operation;
- constraints ensuring unchanged parts of the state remain unchanged, where required for completeness; and
- the relevant output behavior of the processor. [C4]
The evidence gives an ADD-instruction example in which, under the instruction's constraints, the register file is proved to contain the correct updated value one time step later. The forwarding behavior of the pipeline is hidden inside the architectural register-file mapping function. [C4]
Relationship to architectural-style properties and ISS generation
A set of operation properties can resemble a high-level specification, but the corresponding architecture description may remain implicit. For instruction set simulator generation, the cited work reformulates such properties into an architectural style in which the architectural state, interface behavior, reset state, and a next_state macro are explicitly defined. [C5]
In that architectural style, next_state captures the effects of instructions and interrupts on the architectural state. The reformulation supports straightforward generation of an instruction set simulator, because the result is a single property that captures the verified design's behavior using the next_state function and thereby provides a formally checkable ISA description. [C6]
The cited work also states that reformulating operation properties into architectural style does not require a new detailed analysis of the design behavior: identifying architectural-state components and precisely describing instruction semantics are already part of the verification phase. Mapping functions are important for verification, but they are not needed for the automatic ISS generation step. [C7]
Related concepts
- Architectural State: the high-level state representation used by operation properties.
- Mapping Function: the abstraction mechanism that relates architectural state to implementation state.
- Complete Property Suite: the broader verification setting in which completeness requirements require properties to cover unchanged state and output behavior.