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Architectural Style Properties

Concept

Architectural style properties are a formulation of processor verification properties that make the architectural state, interface behavior, reset state, and next-state semantics explicit. In the cited ISS-generation approach, this style turns a formally checked property into a formally checkable ISA description that can be translated into the core of a C++ instruction set simulator.

First seen 5/26/2026
Last seen 5/29/2026
Evidence 4 chunks
Wiki v1

WIKI

Definition

Architectural style properties are verification properties reformulated so that the processor architecture is described explicitly rather than only implicitly through per-operation properties. The cited work introduces this style because an instruction set simulator (ISS) needs an architecture description, mainly an architectural state and a next-state function describing the effects of instructions and interrupts on that state. Operation properties can resemble a high-level specification, but their architecture description is implicit, making generic automatic extraction difficult; architectural style makes ISS generation straightforward. [Architectural-style purpose]

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RELATIONSHIPS

9 connections
Operation Properties extends → 90% 2e
Architectural style properties are a reformulation of operation properties that enable automatic ISS generation.
Mapping Function ← part of 100% 2e
Mapping functions are used in architectural style properties to link implementation state to architectural state.
Architectural State uses → 100% 2e
Architectural style properties are defined in terms of the architectural state.
Complete Property Suite ← uses 100% 2e
The complete property suite is formulated in an architectural style.
Architectural State ← part of 100% 2e
Architectural style properties require explicit modeling of the architectural state.
ITL uses → 100% 2e
Architectural style properties are formulated in the ITL language.
Next State Function ← part of 100% 1e
Architectural style properties include an explicit definition of the next state function.
write_reg macro ← implements 90% 1e
The write_reg macro is used within architectural style properties to specify register updates concisely.
Next State Function uses → 100% 1e
Architectural style properties require an explicit next state function definition.

LINKED ENTITIES

5 links
Instruction Set Simulator enables_generation_of The evidence states that architectural style allows straightforward generation of an ISS and that a C++ ISS is generated from the architectural-style property.
Instruction Set Architecture formalizes The evidence says the architectural-style reformulation yields a formally checkable ISA description.
RTL verified_against The evidence states that the reformulated property is checked against RTL and that gap detection is executed.
Architectural State explicitly_models Architectural style verification is characterized by explicit modeling of the architectural state, represented as a VHDL record containing elements such as registers, flags, and program counter.
Next State Function uses The evidence identifies an explicit next_state macro as a defining feature and says the generated ISA description captures behavior using it.

CITATIONS

12 sources
12 citations — click to expand
[1] Architectural-style purpose Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] Architectural-style characteristics Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] Architectural-state representation Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] Next-state macro role Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[5] Update keyword Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[6] RTL checking and gap detection Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[7] Equivalence proof structure Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[8] ISA description outcome Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[9] Early ISS generation Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[10] No-manual-step generation Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[11] Generated simulator core Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[12] Verified ISS significance Generating an Efficient Instruction Set Simulator from a Complete Property Suite