MINRES The Good Core (TGC)
ToolMINRES The Good Core (TGC) is a MINRES-associated RISC-V RTL processor core/tool represented in the available evidence through a DATE 2022 cross-level processor-verification case study involving an industrial pipelined 32-bit RISC-V processor.
First seen 5/29/2026
Last seen 6/3/2026
Evidence 4 chunks
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WIKI
Overview
MINRES The Good Core (TGC) is represented as a MINRES-associated tool for a RISC-V processor implementation at the Register-Transfer Level (RTL). In the provided evidence, its documented context is processor verification: a DATE 2022 paper on cross-level processor verification reports a case study with an industrial pipelined 32-bit RISC-V processor.
Verification context
NEIGHBORHOOD
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9 connections Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← evaluates 100% 6e
The case study uses the MINRES TGC as the device under test.
TGC is a RISC-V processor implementation
The MINRES TGC is developed by MINRES Technologies GmbH.
MINRES Technologies GmbH developed the TGC series of RISC-V processors.
The MINRES TGC is a 32-bit RISC-V processor implementing the RISC-V ISA.
The MINRES TGC is a pipelined processor.
The TGC is an RTL implementation of a RISC-V processor.
TGC is a pipelined processor
The MINRES TGC is a 32-bit pipelined RISC-V processor.
LINKED ENTITIES
4 linksCross-level processor verification via endless randomized instruction stream generation with coverage-guided aging EVALUATES Extracted graph relationship
MINRES Technologies GmbH PART_OF Extracted graph relationship
RISC-V IMPLEMENTS Extracted graph relationship
Register-Transfer Level (RTL) IMPLEMENTS Extracted graph relationship
CITATIONS
5 sources5 citations — click to expand
[1] The DATE 2022 paper proposes cross-level processor verification at RTL using randomized coverage-guided endless instruction-stream generation and an ISS reference model in tight co-simulation. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[2] The paper uses RISC-V as the representative ISA and describes it as modular, with a mandatory base integer instruction set, optional standard extensions, and support for custom instruction sets. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[3] The paper reports a case study with an industrial pipelined 32-bit RISC-V processor and states that the case study demonstrated the effectiveness of the proposed approach. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] During development of the Coverage-guided Aging test generator, the authors report discovering a micro-architectural-related bug in the accompanied test-bench adapter of an already well-tested industrial RTL core. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[5] The paper lists Eyck Jentzsch as affiliated with MINRES Technologies GmbH. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging