Overview

MINRES The Good Core (TGC) is represented as a MINRES-associated tool for a RISC-V processor implementation at the Register-Transfer Level (RTL). In the provided evidence, its documented context is processor verification: a DATE 2022 paper on cross-level processor verification reports a case study with an industrial pipelined 32-bit RISC-V processor.

Verification context

The DATE 2022 work, Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging, proposes a cross-level verification approach for RTL processor designs. The approach uses a randomized, coverage-guided instruction-stream generator that produces an endless and unrestricted instruction stream evolving at runtime. It also uses an Instruction Set Simulator (ISS) as a reference model in tight co-simulation with the RTL processor under test.

The paper describes RISC-V as the representative ISA for the work and emphasizes its modular structure: a mandatory base integer instruction set, optional standard extensions, and the ability to add custom instruction sets for application-specific processors.

Reported case-study role

The paper reports that its case study used an industrial pipelined 32-bit RISC-V processor and that the study demonstrated the effectiveness of the proposed verification approach. During development of the Coverage-guided Aging test generator, the authors also report finding a micro-architectural-related bug in the accompanied test-bench adapter of an already well-tested industrial RTL core.

Affiliation

The paper lists Eyck Jentzsch as an author affiliated with MINRES Technologies GmbH, connecting the evaluated industrial RISC-V RTL context to MINRES in the provided evidence.