DLX instruction set

Concept

The DLX instruction set is identified in the supplied evidence as the full instruction set implemented by the VAMP processor, attributed to Hennessy and Patterson. In the VAMP case study, it includes load/store operations for multiple data widths, shift operations, jump-and-link operations, and arithmetic and logical operations, with an Isabelle/HOL assembler-level model used to abstract away bit-vector details, address translation, and interrupts.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

The DLX instruction set is described in the evidence as the instruction set implemented by the VAMP processor: “The VAMP implements the full DLX instruction set from Hennessy and Patterson.” [C1]

In that implementation context, the instruction set includes:

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VAMP (Verified Architecture Microprocessor) ← implements 100% 1e

The VAMP implements the full DLX instruction set.

CITATIONS

8 sources

8 citations — click to expand

[1] C1: VAMP implements the full DLX instruction set from Hennessy and Patterson. Test Program Generation for a Microprocessor: A Case Study

[2] C2: The DLX instruction set in the VAMP context includes load/store operations for double words, words, half words, and bytes, as well as shift, jump-and-link, arithmetic, and logical operations. Test Program Generation for a Microprocessor: A Case Study

[3] C3: In the Verisoft project, VAMP was specified in Isabelle/HOL as a programmer’s model with transitions over ISA configurations. Test Program Generation for a Microprocessor: A Case Study

[4] C4: A VAMP ISA configuration consists of pcp, dcp, gprs, sprs, and mm, with the register and memory properties described in the article. Test Program Generation for a Microprocessor: A Case Study

[5] C5: VAMP uses a delayed program-counter mechanism in which pcp fetches the next instruction while dcp remains unchanged until the current instruction completes. Test Program Generation for a Microprocessor: A Case Study

[6] C6: An assembly-language abstraction of the VAMP ISA was introduced to avoid complex bit-vector representations, using natural numbers for addresses and integers for registers and memory contents. Test Program Generation for a Microprocessor: A Case Study

[7] C7: The Isabelle assembler model represents instructions with readable abstract datatypes, hides address translation and interrupts, and uses a linear virtual memory space. Test Program Generation for a Microprocessor: A Case Study

[8] C8: The assembler configuration contains pcp, dcp, gprs, sprs, and mm fields, represented using natural numbers, integer lists, and a mapping from naturals to integers. Test Program Generation for a Microprocessor: A Case Study