Overview
The DLX instruction set is described in the evidence as the instruction set implemented by the VAMP processor: “The VAMP implements the full DLX instruction set from Hennessy and Patterson.” [C1]
In that implementation context, the instruction set includes:
- load and store operations for double words, words, half words, and bytes;
- different shift operations;
- jump-and-link operations;
- various arithmetic and logical operations. [C2]
VAMP implementation context
The supplied evidence discusses DLX through the VAMP processor model developed in the context of the Verisoft project. The VAMP processor is specified in Isabelle/HOL as a programmer’s model consisting of transitions over Instruction Set Architecture configurations. [C3]
A VAMP ISA configuration is composed of five elements:
pcp, a 30-bit program-counter register containing the address of the next instruction to be executed;dcp, a 30-bit delayed program-counter register containing the currently executed instruction;gprs, a general-purpose register file with 32 32-bit registers, indexed from 0 to 31, with the first register always set to 0;sprs, a special-purpose register file with 32 32-bit registers, including registers used for status, flags, or conditions;mm, a memory model described as a 2^32-byte addressable memory. [C4]
The evidence also notes that VAMP uses a delayed program-counter mechanism: while the next instruction is fetched using pcp, dcp is kept unchanged until the current instruction finishes execution. [C5]
Assembler-level abstraction
To avoid a complex bit-vector representation of data and instructions, the VAMP case study introduced an assembly-language abstraction of the VAMP ISA. In this assembler model, addresses are represented by natural numbers, while registers and memory contents are represented by integers. [C6]
The Isabelle theory of this assembler model abstracts the instruction-set architecture further. Instructions are represented as an abstract datatype with readable names; address translation is not visible; assembler computations occur in a linear virtual memory space; and interrupts are not visible at this level. [C7]
The assembler configuration is represented as a record with fields for the program counters, register files, and memory model:
pcp: natural-number program counter;dcp: natural-number delayed program counter;gprs: list of integers for the general-purpose register file;sprs: list of integers for the special-purpose register file;mm: memory model mapping natural numbers to integers. [C8]
Technical significance in the evidence
Within the supplied material, DLX is primarily significant as the instruction set used by VAMP and as the target of an assembler-level formal model. The evidence connects the instruction set to formal verification and test-program generation work by describing how DLX-level program behavior is modeled through ISA configurations and then abstracted into a more convenient assembler representation. [C1] [C3] [C6]