Definition
A program counter is a processor state element used to identify the instruction address involved in execution. In architectural-style processor models, the architectural state is commonly represented as a record combining state components such as a register file, status flags, and a program counter. [C1]
VAMP processor model
In the VAMP Instruction Set Architecture (ISA) configuration, the program counter is named pcp. It is a 30-bit register containing the address of the next instruction to be executed. The VAMP model uses this register to fetch an instruction without altering execution of the current instruction; the cited case study calls this pipelining mechanism delayed pc. [C2]
The VAMP ISA configuration also includes a delayed program counter, named dcp. The dcp is described as a 30-bit register for the delayed program counter and as containing the currently executed instruction. While the next instruction is fetched through pcp, dcp remains unchanged until the end of execution of the current instruction. [C3]
Place in architectural state
The VAMP programmer's model defines processor behavior as transitions over ISA configurations. Each configuration is composed of five elements: the program counter, the delayed program counter, general-purpose registers, special-purpose registers, and a memory model. [C4]
This aligns with the broader architectural-modeling view in which the architectural state explicitly captures processor state components and a next_state function captures the effects of instructions and interrupts on that architectural state. [C5]
Assembler-level abstraction
The VAMP assembler model abstracts the ISA model. In this abstraction, addresses are represented by natural numbers, and the assembler configuration includes pcp as a natural number representing the program counter. The same abstraction includes dcp as a natural number representing the delayed program counter. [C6]
Implementation variants
Program counters are commonly implemented as conventional radix-2 counters, but FPGA-oriented research has compared them with program counters based on feedback shift registers (FSRs). The cited work reports that FSR counters have constant-time scaling with bit width, whereas FPGA radix-2 counters typically scale with the carry chain, and it presents hybrid FSR/radix-2 counters as a response to potential cache-coherency issues. [C7]