SystemVerilog HDL
ConceptSystemVerilog HDL appears in the ProcessorFuzz evidence as a hardware description language relevant to RTL processor verification. The cited work highlights a tooling limitation: attempted SystemVerilog-to-FIRRTL conversion had limited support and failed to instrument BlackParrot.
First seen 5/28/2026
Last seen 6/8/2026
Evidence 12 chunks
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Overview
SystemVerilog HDL is a hardware description language referenced in the ProcessorFuzz paper in the context of Register-Transfer Level (RTL) processor verification. The paper frames hardware fuzzing as a method for verifying RTL designs and notes that prior works can suffer from limited support for widely used hardware description languages.
Role in ProcessorFuzz evaluation
NEIGHBORHOOD
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6 connectionsSystemVerilog HDL is one of the Hardware Description Languages mentioned in the paper.
BlackParrot is designed in SystemVerilog HDL.
BlackParrot Core is designed in SystemVerilog HDL.
Yosys is used to convert SystemVerilog designs to FIRRTL.
BlackParrot Core is designed in SystemVerilog HDL.
SystemVerilog is one of the HDLs used in the evaluated processors.
CITATIONS
3 sources3 citations — click to collapse
[1] ProcessorFuzz is presented as a processor fuzzer for RTL verification that uses CSR-transition coverage, and it was evaluated on Rocket, BOOM, and BlackParrot. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
[2] Prior processor-fuzzing work is described as suffering from limitations including lack of support for widely used hardware description languages. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
[3] Limited SystemVerilog-to-FIRRTL conversion support caused issues and led to failure to instrument BlackParrot. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance