Chipyard

Tool

Chipyard is an agile, open-source RISC-V SoC design framework written in Scala that supports in-order cores, out-of-order cores, accelerators, and peripherals. It is hosted at the ucb-bar/chipyard GitHub repository and is widely used in research on functional verification, test generation, and security of RISC-V processors.

First seen 6/19/2026

Last seen 6/24/2026

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Chipyard

Overview

Chipyard is an agile RISC-V SoC design framework developed by the UC Berkeley BAR group. The upstream repository ucb-bar/chipyard is described as an "Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more," and the codebase is primarily written in Scala [ucb-bar/chipyard].

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RELATIONSHIPS

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A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors ← uses 95% 2e

The paper uses Chipyard as a key SoC generation framework for SLT research.

SoC Generation Framework implements → 100% 2e

Chipyard is an open-source SoC generation framework.

Rocket Chip Generator uses → 90% 1e

Chipyard supports configuration of SoCs based on the Rocket core.

BOOM (Berkeley Out-of-Order Machine) uses → 90% 1e

Chipyard supports configuration of SoCs based on the BOOM out-of-order core.

CVA6 (Ariane) uses → 90% 1e

Chipyard supports configuration of SoCs based on CVA6.

Cascade ← uses 65% 1e

The instructions reference a cascade-chipyard repository used to build and simulate the Rocket core.

Ibex uses → 90% 1e

Chipyard supports configuration of SoCs based on Ibex.

Fuzzing for Test Generation ← uses 85% 1e

Chipyard supports fuzzing by providing bus monitors to observe activity and guide fuzzer feedback.

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CITATIONS

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4 citations — click to collapse

[1] Chipyard is an agile RISC-V SoC design framework with in-order cores, out-of-order cores, accelerators, and more, written in Scala, hosted at ucb-bar/chipyard. ucb-bar/chipyard (GitHub repository metadata)

[2] Chipyard allows freely configuring SoCs based on in-order cores (Rocket, CVA6, Ibex, Sodor) or out-of-order cores (BOOM), with configurable caches, issue widths, reorder buffer sizes, 32/64-bit selection, and extensions. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

[3] Chipyard is cited in verification literature for SBST/STL/Burn-In approaches for RISC-V with extensions and for CHERI-with-security-extension verification using TestRIG with QuickCheck VEngine over RVFI and DII sockets. Survey of Verification of RISC-V Processors (Journal of Electronic Testing 2025)

[4] Cascade plugs into Chipyard via a `cascade-chipyard` directory and uses `cascade_meta/design_processing/design_repos.json` to configure the Rocket core entry for Questasim experiments. comsec-group/cascade-artifacts (GitHub repository)