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Chipyard

Tool WIKI v1 · 6/24/2026

Chipyard is an agile, open-source RISC-V SoC design framework written in Scala that supports in-order cores, out-of-order cores, accelerators, and peripherals. It is hosted at the ucb-bar/chipyard GitHub repository and is widely used in research on functional verification, test generation, and security of RISC-V processors.

Chipyard

Overview

Chipyard is an agile RISC-V SoC design framework developed by the UC Berkeley BAR group. The upstream repository ucb-bar/chipyard is described as an "Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more," and the codebase is primarily written in Scala [ucb-bar/chipyard].

Key repository metadata from the public GitHub source:

  • Language: Scala
  • Stars: 2,298
  • Forks: 877
  • Last updated: 2026-06-24 [ucb-bar/chipyard]

Core Capabilities

Chipyard provides a highly configurable SoC generation environment. According to a published survey on RISC-V testing, safety, and security, Chipyard allows researchers to:

  • Configure SoCs based on in-order cores such as Rocket, CVA6, Ibex, and an educational core called Sodor, or out-of-order cores such as BOOM, and even mix both styles [ETS_RISC_V_testing_safety_security].
  • Add or remove caches, change cache sizes, and modify aspects of cores such as the number of issues in the BOOM core and the size of the reorder buffer [ETS_RISC_V_testing_safety_security].
  • Enable or disable ISA extensions and choose between a 32-bit and 64-bit architecture [ETS_RISC_V_testing_safety_security].
  • Use a wide range of well-tested peripherals to test interactions between the core and the periphery [ETS_RISC_V_testing_safety_security].
  • Add custom peripherals and modify existing ones (e.g., bus monitors) to observe activity on buses and provide feedback to fuzzers or other greybox monitors [ETS_RISC_V_testing_safety_security].

The same survey notes that, because several Chipyard designs are compatible with traditional ASIC design flows, additional information such as power simulations, FPGA-mapped emulation, and bus-monitor outputs can be extracted [ETS_RISC_V_testing_safety_security].

Use in Verification and Testing Research

Chipyard appears in the verification literature as an enabling platform for testing RISC-V processors:

  • A 2025 Journal of Electronic Testing survey reports an entry for a "RISC-V base with any extensions" system using a Software-based Self-Test (SBST) approach with Self Test Libraries (STL) and Burn-In (BI) programs, citing Chipyard as the underlying framework [Survey_Verification_RISC_V].
  • The same survey describes a CHERI-with-security-extension case that uses Chipyard together with TestRIG and QuickCheck VEngine to communicate over RVFI and DII sockets to exhaustively test faulty instructions in a pipeline, discovering cache bugs and memory mistakes [Survey_Verification_RISC_V].
  • The ETS survey highlights Chipyard as a flexible platform for analyzing multiple architectures when developing automated methods to generate Software-based Self-Test (SLT) programs targeting non-functional properties [ETS_RISC_V_testing_safety_security].

Use in Security and Fuzzing Research

Chipyard is used as the underlying SoC platform for the Cascade security research artifacts. The Cascade documentation describes a forked layout in which the Chipyard tree is embedded as cascade-chipyard, and includes the following commands for building the Rocket core for Questasim simulation [comsec-group/cascade-artifacts]:

source /path/to/cascade-meta && cd /path/to/cascade-chipyard/cascade && make build_vanilla_notrace_modelsim && make rerun_vanilla_notrace_modelsim

The same documentation notes that users may have to adapt the rocket entry in the local cascade_meta/design_processing/design_repos.json for running the experiment, indicating that Cascade plugs into Chipyard's design processing configuration [comsec-group/cascade-artifacts].

Relationships with Other Tools

  • Cascade uses Chipyard as its underlying SoC generation framework (the Chipyard tree is incorporated as cascade-chipyard) [comsec-group/cascade-artifacts].

See Also

References

  1. ucb-bar/chipyard — GitHub repository, https://github.com/ucb-bar/chipyard
  2. comsec-group/cascade-artifacts — GitHub repository, https://github.com/comsec-group/cascade-artifacts
  3. "Survey of Verification of RISC-V Processors" — Journal of Electronic Testing (2025) 41:111–138, https://d-nb.info/1375027034/34
  4. "A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors" — Politecnico di Torino IRIS, https://iris.polito.it/bitstream/11583/2978944/1/ETS_RISC_V_testing_safety_security.pdf

LINKED ENTITIES

1 links
Cascade USES

CITATIONS

4 sources
4 citations
[1] Chipyard is an agile RISC-V SoC design framework with in-order cores, out-of-order cores, accelerators, and more, written in Scala, hosted at ucb-bar/chipyard. ucb-bar/chipyard (GitHub repository metadata)
[2] Chipyard allows freely configuring SoCs based on in-order cores (Rocket, CVA6, Ibex, Sodor) or out-of-order cores (BOOM), with configurable caches, issue widths, reorder buffer sizes, 32/64-bit selection, and extensions. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
[3] Chipyard is cited in verification literature for SBST/STL/Burn-In approaches for RISC-V with extensions and for CHERI-with-security-extension verification using TestRIG with QuickCheck VEngine over RVFI and DII sockets. Survey of Verification of RISC-V Processors (Journal of Electronic Testing 2025)
[4] Cascade plugs into Chipyard via a `cascade-chipyard` directory and uses `cascade_meta/design_processing/design_repos.json` to configure the Rocket core entry for Questasim experiments. comsec-group/cascade-artifacts (GitHub repository)