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Ibex

Tool WIKI v1 · 5/30/2026

Ibex is a small 32-bit RISC-V CPU core, formerly known as zero-riscy. Its public repository is primarily SystemVerilog, and it is listed among TestRIG-compatible RISC-V implementations used in randomized CPU testing research.

Overview

Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy. Its public lowRISC/ibex repository identifies the implementation language as SystemVerilog. As of the provided GitHub metadata, the repository had 1,892 stars, 741 forks, and was updated on 2026-05-28.

Role in RISC-V testing

The TestRIG paper lists Ibex among RISC-V implementations in its ecosystem, alongside RVBS, Piccolo, Flute, and Toooba. In that context, Ibex and Piccolo are described as simple 32-bit implementations. The same paper states that TestRIG-compatible implementations participate through RVFI-DII instrumentation and are expected to provide a standardized architectural environment, including reset behavior and an 8 MiB memory region at address 0x80000000.

Technical characterization

From the available evidence, Ibex can be characterized as:

  • a 32-bit RISC-V CPU core;
  • implemented in SystemVerilog according to the public repository metadata;
  • formerly named zero-riscy;
  • included among implementations compatible with the TestRIG randomized RISC-V CPU testing ecosystem.

LINKED ENTITIES

3 links
TestRIG EVALUATES
RISC-V IMPLEMENTS
SystemVerilog USES

CITATIONS

5 sources
5 citations
[1] Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy. lowRISC/ibex
[2] The public Ibex repository metadata identifies SystemVerilog as the repository language and reports 1,892 stars, 741 forks, and an update time of 2026-05-28T16:04:10Z. lowRISC/ibex
[3] The TestRIG paper lists Ibex among implementations in the TestRIG ecosystem and describes Ibex and Piccolo as simple 32-bit implementations. Randomized Testing of RISC-V CPUs using Direct
[4] TestRIG-compatible implementations use RVFI-DII instrumentation and are expected to provide a common architectural environment including reset behavior and an 8 MiB memory region at address 0x80000000. Randomized Testing of RISC-V CPUs using Direct
[5] The TestRIG repository collates TestRIG-compatible implementations and verification engines and is intended to support standardized RISC-V testing based on instrumentation of open implementations. Randomized Testing of RISC-V CPUs using Direct