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Golden model ISS

Concept WIKI v1 · 6/6/2026

In the Ibex core verification flow, a golden model ISS is a reference Instruction Set Simulator whose execution trace is compared against the RTL core's trace to determine simulation correctness. It is used as the trusted reference inside the end-to-end RTL/ISS co-simulation flow, primarily for register writeback comparison, and is supplemented by the RISCV-DV handshaking mechanism for scenarios involving external stimulus.

Overview

In the Ibex core verification environment, a golden model ISS (Instruction Set Simulator) is a trusted software reference model whose behavior is compared against the RTL implementation of the core to determine whether a given simulation produces a correct result. It is the last-stage reference in the end-to-end RTL/ISS co-simulation flow, where the trace log produced by the core and the trace log produced by the chosen golden model ISS are both parsed and compared.

Role in the co-simulation flow

Within the end-to-end RTL/ISS co-simulation flow, the golden model ISS serves as the correctness oracle. Both the core's trace log and the ISS's trace log are parsed to collect information about all register writebacks that occur. The two sets of register writeback data are then compared to verify that the core is writing:

  • the correct data,
  • to the correct registers,
  • in the correct order.

This per-writeback comparison forms the primary correctness check for simulation results when no external stimulus is involved.

Limitations regarding external stimulus

The straightforward register writeback comparison breaks down once situations involving external stimulus — such as interrupts and debug requests — are tested. While ISS models can simulate traps due to exceptions, they cannot model traps due to external stimulus. This means an ISS-only comparison cannot, on its own, verify whether the core has entered the proper interrupt handler, entered Debug Mode properly, or updated any CSRs correctly in response to an external trigger.

Complementary handshaking mechanism

To provide coverage for these external-stimulus scenarios, the RISCV-DV handshaking mechanism is used heavily. This mechanism effectively allows the core to send status information to the testbench during program execution so that any required analysis can be performed to increase verification effectiveness. The signature address used by the Ibex testbench for this handshaking is 0x8ffffffc. The handshaking mechanism is extensively used to provide runtime verification for situations involving external debug requests, interrupt assertions, and memory faults.

Modified trace comparison for stimulus-bearing tests

As an additional layer of correctness checking on top of the handshaking mechanism, a modified version of the trace log comparison is applied. Comparing every register write performed during the entire simulation would lead to incorrect results, because the ISS trace log will not contain any execution information in the debug ROM or in any interrupt handler code. Therefore, only the final values contained in every register at the end of the test are compared between the core and the golden model ISS. Code executed in the debug ROM and trap handlers is not expected to corrupt register state in the rest of the program, so end-of-test register state comparison remains a valid check.

Related concepts

  • RTL/ISS co-simulation — the verification flow in which the golden model ISS is consumed as the reference model.

LINKED ENTITIES

1 links
RTL/ISS co-simulation USES

CITATIONS

7 sources
7 citations
[1] A golden model ISS is used as the reference model in the end-to-end RTL/ISS co-simulation flow, where both the core's trace log and the ISS's trace log are parsed to collect register writeback information and compared for correctness. Verification — Ibex Documentation
[2] The trace log comparison verifies that the core writes the correct data to the correct registers in the correct order. Verification — Ibex Documentation
[3] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus such as interrupts and debug requests. Verification — Ibex Documentation
[4] The RISCV-DV handshaking mechanism is used to let the core send status information to the testbench during program execution, enabling verification of interrupt handler entry, Debug Mode entry, and CSR updates. Verification — Ibex Documentation
[5] The signature address used by the Ibex testbench for the RISCV-DV handshaking is 0x8ffffffc. Verification — Ibex Documentation
[6] The handshaking mechanism is extensively used to provide runtime verification for external debug requests, interrupt assertions, and memory faults. Verification — Ibex Documentation
[7] Because the ISS trace log will not contain any execution information in the debug ROM or in any interrupt handler code, only the final values contained in every register at the end of the test are compared between the core and the golden model ISS. Verification — Ibex Documentation