Instruction Issue Unit

Concept

The Instruction Issue Unit is the issue stage of a two-way superscalar out-of-order RISC-V processor. It receives renamed instructions from the Issue Queue, uses scoreboard state to identify ready instructions, and can dispatch up to two ready instructions per cycle subject to functional-unit availability, instruction validity, and dual-issue dependency constraints.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

The Instruction Issue Unit corresponds to the Instruction Issue (IS) stage in the described two-way superscalar out-of-order RISC-V processor. After instructions are fetched, decoded, and register-renamed, the renamed instructions enter the Issue Queue and pass through the IS stage. The IS stage uses a scoreboard to track the status of each physical register and, based on that information, may issue up to two ready instructions per cycle for out-of-order execution.

Role in the pipeline

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

Superscalar Out-of-Order Processor part of → 98% 1e

The instruction issue unit is part of the superscalar out-of-order processor.

LINKED ENTITIES

1 links

Superscalar Out-of-Order Processor PART_OF Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] The Instruction Issue stage receives renamed instructions from the Issue Queue, uses a scoreboard to track physical-register status, and can issue up to two ready instructions per cycle for out-of-order execution. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The Issue stage is positioned after Register Renaming and before the Execution stage in the described processor pipeline. [PDF] UVM-based verification of RISC-V superscalar processors

[3] Issue-time checks include functional-unit availability and instruction validity. [PDF] UVM-based verification of RISC-V superscalar processors

[4] To issue a second instruction in the same cycle, the two instructions must target different functional units and the second instruction's source operands must not depend on the first instruction's destination operand. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The Execution stage contains the Integer ALU, Branch Resolve Unit, and Load-Store Unit, with differing latency and busy behavior relevant to instruction acceptance. [PDF] UVM-based verification of RISC-V superscalar processors