Overview

The Instruction Issue Unit corresponds to the Instruction Issue (IS) stage in the described two-way superscalar out-of-order RISC-V processor. After instructions are fetched, decoded, and register-renamed, the renamed instructions enter the Issue Queue and pass through the IS stage. The IS stage uses a scoreboard to track the status of each physical register and, based on that information, may issue up to two ready instructions per cycle for out-of-order execution.

Role in the pipeline

In the processor organization described by the evidence, the Instruction Issue Unit sits after Register Renaming and before the Execution stage. Register Renaming maps architectural registers to physical registers to remove name dependencies, and the Issue stage then decides which renamed instructions are ready to proceed to execution.

The unit is part of a two-way superscalar out-of-order core: the front end can fetch and decode two instructions per cycle, Register Renaming can rename up to two instructions per cycle, and the Issue stage can issue up to two ready instructions per cycle.

Readiness and issue checks

The Issue stage relies on scoreboard information about physical-register readiness. The evidence also identifies issue-time checks including whether the destination functional unit is available to receive the instruction and whether the instruction is valid.

For issuing a second instruction in the same cycle, additional dual-issue constraints apply:

• the two instructions must use different functional units; and
• the source operands of the second instruction must not depend on the destination operand of the first instruction.

These constraints prevent the same-cycle pair from conflicting on a functional unit or introducing an immediate dependency from the first issued instruction to the second.

Interaction with execution resources

The Execution stage contains the functional units that receive issued operations: an Integer ALU, a Branch Resolve Unit, and a Load-Store Unit. Functional-unit behavior affects whether an instruction can be accepted. For example, division keeps the Integer ALU busy for multiple cycles, multiplication is fully pipelined with a later result, branch-resolve operations complete in one cycle and the branch unit is described as never appearing busy, and the Load-Store Unit is a two-cycle pipelined module.