reorder buffer — STIMSMITH

ReOrder Buffer (ROB)

Concept

A ReOrder Buffer (ROB) is a processor microarchitectural structure used in superscalar out-of-order designs to hold execution results until instructions can retire in program order. In the provided RISC-V superscalar processor evidence, the ROB is a cyclic buffer that accepts up to two renamed instructions per cycle, tracks completion from functional units, commits the oldest ready entries in order, and helps make store instructions non-speculative only when they reach the ROB head. It is also a practical observation and perturbation point in processor verification co-simulation and logic fuzzing.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

A ReOrder Buffer (ROB, also written as Reorder Buffer or Re-Order Buffer) is a microarchitectural structure in the back end / write-back portion of an out-of-order processor. In the provided two-way RISC-V superscalar out-of-order processor, execution results are temporarily stored in the ROB until their instructions can commit or retire. The ROB maintains correct program order during retirement even though execution may complete out of order, and it supports speculative execution beyond branches. [C1]

Operation in a two-way superscalar out-of-order core

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NEIGHBORHOOD

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RELATIONSHIPS

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Logic Fuzzer ← uses 100% 2e

Logic Fuzzer applies congestors to the reorder buffer's ready signal.

congestor ← uses 95% 1e

A congestor was inserted at the ready signal of the Reorder Buffer in BOOM.

Superscalar Out-of-Order Processor part of → 98% 1e

The ReOrder Buffer is a component of the superscalar out-of-order processor.

LINKED ENTITIES

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Superscalar Out-of-Order Processor PART_OF Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] The ROB temporarily stores execution results until commit/retirement, maintains correct program order during retirement despite out-of-order execution, supports speculative execution beyond branches, and up to two instructions can commit per cycle in the described two-way RISC-V processor. [PDF] UVM-based verification of RISC-V superscalar processors

[2] In the described design, the ROB is a cyclic buffer that can receive up to two new data-store requests per cycle from renamed instructions and can reserve up to two entries per cycle. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The ROB checks the two oldest entries each cycle, and commits happen in order even though execution can complete out of order. [PDF] UVM-based verification of RISC-V superscalar processors

[4] Functional-unit completion data is written into the selected ROB entry using a ticket, and the pending bit is deasserted when execution is complete. [PDF] UVM-based verification of RISC-V superscalar processors

[5] The ROB tracks speculative instructions; stores may modify cache contents only after becoming non-speculative at the ROB head, and loads can check for forwarding from the ROB. [PDF] UVM-based verification of RISC-V superscalar processors

[6] Instruction Fetch, Register Renaming, Issue, and ReOrder Buffer are listed as verified units in the RISC-V superscalar processor verification work. [PDF] UVM-based verification of RISC-V superscalar processors

[7] For BOOM-Dromajo co-simulation, monitor logic in the Reorder Buffer can call Dromajo's DPI step function when the ROB head instruction is valid and ready to commit; Dromajo then commits one instruction and compares communicated data. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[8] Logic Fuzzer can perturb ROB full, stall, or ready behavior without corrupting functionality or program order; a BOOM ready-signal congestor produced additional frontend, core, and load-store-unit toggle activity. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[9] The SPECRUN public summary states that the attack eliminates the limitation on the number of transient instructions posed by reorder-buffer size. SPECRUN: The Danger of Speculative Runahead Execution in Processors

[10] The public summary of the I2E memory-model paper identifies the reorder buffer as a microarchitectural detail, along with partial/speculative execution and instruction replay, that complicates formal memory-model reasoning. An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution