congestor

Technique

A congestor is a Logic Fuzzer technique for processor RTL verification that injects artificial backpressure by randomly perturbing congestion-related control signals such as FIFO full, ready, busy, or ready-valid handshake signals.

First seen 5/28/2026

Last seen 5/28/2026

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WIKI

Overview

A congestor is described as the simplest type of Logic Fuzzer. It is inserted into RTL control logic to create artificial congestion or backpressure while the same verification binaries continue to run. A canonical example is adding an OR gate at a FIFO full signal so that full can be asserted even when the FIFO is not actually full; random activation of this inserted logic produces artificial backpressure. The same idea can also be applied at busy signals and ready-valid handshake signals. [C1]

Purpose

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NEIGHBORHOOD

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RELATIONSHIPS

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Logic Fuzzer ← implements 100% 2e

The Logic Fuzzer implements congestors as one of its fuzzing techniques.

FIFO uses → 95% 2e

Congestors are applied to FIFO full/ready signals to create artificial backpressure.

reorder buffer uses → 95% 1e

A congestor was inserted at the ready signal of the Reorder Buffer in BOOM.

toggle coverage uses → 90% 1e

Toggle coverage is used to measure the effect of congestors on signal activation.

LINKED ENTITIES

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Logic Fuzzer IMPLEMENTS Extracted graph relationship

FIFO USES Extracted graph relationship

reorder buffer USES Extracted graph relationship

toggle coverage USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] A congestor is the simplest type of Logic Fuzzer; an example places inserted logic at a FIFO full signal to randomly create artificial backpressure, and congestors can also be located at busy and ready-valid handshake signals. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[2] The evaluation compares a base Dromajo-enabled setup against runs with Logic Fuzzers enabled, where the fuzzers expose additional bugs. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[3] Logic Fuzzer may create microarchitectural states unreachable by real programs, but co-simulation failures from fuzzing are treated as potential bugs; the paper's presented bugs were confirmed by designers. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[4] For congestor implementation, engineers identify congestible points, configure the fuzzer object to create the same number of congestor objects, and set each congestor's period and random seeds in a JSON file. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[5] A proof-of-concept automatic insertion flow for BOOM used RTL signal annotations and Chiffre to break the annotated signal and insert the congestor. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[6] Toggle coverage is used to observe additional activity after congestor insertion; a signal is considered toggled if it switches 0→1 and 1→0 at least once during the test. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[7] In BOOM, inserting a congestor at the Reorder Buffer ready signal and randomly pulling it low caused 12 additional frontend, 40 core, and 32 load-store-unit signals to toggle, demonstrating that one congestor activated logic not touched by over 200 tests. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[8] In BlackParrot, a congestor at a frontend-backend FIFO ready signal exposed a bug where artificial backpressure led to wrong-PC instruction commits because backend commands could be lost when the queue was not ready. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...