Toooba
ToolToooba is an open-source Bluespec/Verilog RISC-V core described as superscalar, out-of-order, and multi-core capable. It has been instrumented for TestRIG-style RVFI-DII verification, including changes to support direct instruction injection, superscalar fetch, compressed instruction fragments, and RVFI reporting.
First seen 5/30/2026
Last seen 6/8/2026
Evidence 15 chunks
Wiki v1
WIKI
Overview
Toooba is an open-source RISC-V core from Bluespec. The public GitHub description characterizes it as a superscalar, out-of-order, multi-core-capable RISC-V core based on MIT's RISCY-OOO design. The repository is listed as Verilog and, in the provided public metadata, has 187 stars, 51 forks, and was updated on 2026-05-20.
Microarchitecture role
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
10 connectionsTestRIG is used to test the Toooba processor, including CHERI extensions and lockup bugs.
Toooba is a RISC-V out-of-order processor derived from RiscyOO.
Toooba is extended with CHERI modifications as the first open superscalar CHERI implementation.
Toooba is a fork of RiscyOO and implements superscalar out-of-order execution.
Toooba is used as a platform to research and implement temporal safety with CHERI.
The thesis evaluates the CHERI-extended Toooba superscalar processor.
Toooba is implemented in Bluespec HDL as a fork of RiscyOO.
Toooba is evaluated in the context of safe speculation for CHERI processors.
Toooba is a fork of the RiscyOO processor from MIT, extended with CHERI modifications.
Toooba as an application-class processor uses virtual memory via an MMU.
CITATIONS
6 sources6 citations — click to expand
[1] Toooba is a Bluespec open-source RISC-V core described as superscalar, out-of-order, multi-core capable, and based on MIT's RISCY-OOO. bluespec/Toooba
[2] The Toooba repository public metadata identifies the language as Verilog, with 187 stars, 51 forks, and an updated_at timestamp of 2026-05-20T07:06:37Z. bluespec/Toooba
[3] TestRIG extends RVFI with Direct Instruction Injection, where DII is used for instruction input and RVFI for trace output, enabling interactive verification. Randomized Testing of RISC-V CPUs using Direct
[4] For superscalar Toooba, RVFI-DII work first substituted the vector of picked instructions before decode while keeping instruction-cache access, then moved to bypassing the instruction cache and providing 16-bit instruction fragments to exercise instruction picking and decode. Randomized Testing of RISC-V CPUs using Direct
[5] The RVFI-DII approach adapted to Toooba added superscalar fetch and assigned IDs to compressed instruction fragments to keep DII/RVFI synchronization through pipeline effects. Randomized Testing of RISC-V CPUs using Direct
[6] Extending the superscalar Toooba core for RVFI-DII required two extra records per instruction in the reorder buffer, present only when built for simulation with RVFI and therefore not a physical overhead for the design. Randomized Testing of RISC-V CPUs using Direct