Skip to content
STIMSMITH

Toooba

Tool WIKI v1 · 5/30/2026

Toooba is an open-source Bluespec/Verilog RISC-V core described as superscalar, out-of-order, and multi-core capable. It has been instrumented for TestRIG-style RVFI-DII verification, including changes to support direct instruction injection, superscalar fetch, compressed instruction fragments, and RVFI reporting.

Overview

Toooba is an open-source RISC-V core from Bluespec. The public GitHub description characterizes it as a superscalar, out-of-order, multi-core-capable RISC-V core based on MIT's RISCY-OOO design. The repository is listed as Verilog and, in the provided public metadata, has 187 stars, 51 forks, and was updated on 2026-05-20.

Microarchitecture role

Toooba is explicitly referred to in the TestRIG paper as a superscalar core. In the public repository summary, it is also described as out-of-order, so it is best categorized as an implementation of a superscalar out-of-order RISC-V processor design.

RVFI-DII and TestRIG instrumentation

The TestRIG work extends the RISC-V Formal Interface (RVFI) with Direct Instruction Injection (DII). In that setup, DII provides instruction input and RVFI provides trace output, enabling interactive verification with trace comparison, simplification, and shrinking.

Toooba was one of the RTL designs adapted for RVFI-DII. For superscalar Toooba, the authors initially kept the normal instruction-cache access path and substituted the vector of picked instructions before decode. To debug instruction picking, they later bypassed the instruction cache and injected 16-bit instruction fragments into the pipeline, relying on instruction picking and decode logic to reconstruct the intended DII instruction stream.

The TestRIG paper also describes a synchronization strategy for dropped or canceled instructions: each injected instruction needs a corresponding RVFI trace entry. The approach adapted to Toooba adds superscalar fetch and assigns sequence IDs to compressed instruction fragments, allowing the DII unit to track instruction flow through redirects and pipeline effects.

RVFI reporting overhead in simulation builds

Adding RVFI-DII support to the superscalar Toooba core required preserving additional state for RVFI reporting at commit/write-back. Specifically, the paper states that Toooba required two extra records per instruction in the reorder buffer. These records are present only in simulation builds with RVFI enabled, so the authors state that this is not a physical overhead for the design.

LINKED ENTITIES

2 links
TestRIG EVALUATES
Superscalar Out-of-Order Processor IMPLEMENTS

CITATIONS

6 sources
6 citations
[1] Toooba is a Bluespec open-source RISC-V core described as superscalar, out-of-order, multi-core capable, and based on MIT's RISCY-OOO. bluespec/Toooba
[2] The Toooba repository public metadata identifies the language as Verilog, with 187 stars, 51 forks, and an updated_at timestamp of 2026-05-20T07:06:37Z. bluespec/Toooba
[3] TestRIG extends RVFI with Direct Instruction Injection, where DII is used for instruction input and RVFI for trace output, enabling interactive verification. Randomized Testing of RISC-V CPUs using Direct
[4] For superscalar Toooba, RVFI-DII work first substituted the vector of picked instructions before decode while keeping instruction-cache access, then moved to bypassing the instruction cache and providing 16-bit instruction fragments to exercise instruction picking and decode. Randomized Testing of RISC-V CPUs using Direct
[5] The RVFI-DII approach adapted to Toooba added superscalar fetch and assigned IDs to compressed instruction fragments to keep DII/RVFI synchronization through pipeline effects. Randomized Testing of RISC-V CPUs using Direct
[6] Extending the superscalar Toooba core for RVFI-DII required two extra records per instruction in the reorder buffer, present only when built for simulation with RVFI and therefore not a physical overhead for the design. Randomized Testing of RISC-V CPUs using Direct