Lyra
ToolFirst seen 6/10/2026
Last seen 6/10/2026
Evidence 11 chunks
NEIGHBORHOOD
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21 connectionsLyra executes and verifies the DUT on FPGA.
Lyra uses LyraGen as its generative model for instruction generation.
Lyra implements the generative model-based processor fuzzing approach.
Lyra offloads verification to FPGA for hardware acceleration.
Lyra performs hardware-level differential checking between DUT and reference model.
Lyra uses the register coverage metric for coverage collection on FPGA.
Lyra includes an instruction legality checker to validate generated instructions.
Lyra includes an address correction module to prevent invalid memory accesses.
Lyra's differential checking module is based on the ENCORE structure.
Lyra is empirically compared against DifuzzRTL in coverage and throughput.
Lyra is empirically compared against Cascade in coverage and throughput.
Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing ← introduces 100% 2e
The paper presents Lyra as its primary contribution.
Lyra targets accelerating coverage convergence as a key goal.
Lyra generates high-quality instruction stimuli using its generative model.
Lyra generates training data using hardware fuzzing as an initial stimulus.
Lyra exploits ISA semantics for instruction generation and verification.
Lyra runs the reference model concurrently with the DUT for differential checking.
Lyra uses RocketCore as the DUT for all experiments.
Lyra is a RISC-V verification framework.
Lyra incorporates RTL-level coverage instrumentation methods.
Lyra incorporates control register-based coverage instrumentation.