AHB Verification IP

Concept

AHB Verification IP is identified in the provided evidence as a verification component or topic within the paper/thesis "UVM based design verification of a RISC-V CPU core," where it appears as section 4.2.4 before the scoreboard, Spike instruction set simulator, and coverage model sections.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

AHB Verification IP is referenced in the provided evidence as a distinct subsection, "4.2.4 AHB verification IP," in the paper/thesis "UVM based design verification of a RISC-V CPU core." The table of contents places this subsection on page 51, within a larger verification-environment discussion that also includes a scoreboard, the Spike instruction set simulator, and a coverage model.

Role in the cited RISC-V verification work

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NEIGHBORHOOD

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RELATIONSHIPS

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UVM Based Design Verification of a RISC-V CPU Core ← uses 90% 1e

The paper includes AHB verification IP in its testbench architecture.

LINKED ENTITIES

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] The paper/thesis "UVM based design verification of a RISC-V CPU core" contains a section titled "4.2.4 AHB verification IP" on page 51. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The AHB verification IP section is listed near other verification-environment sections, including Scoreboard, Spike instruction set simulator, and Coverage model. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The available evidence does not provide the body text of the AHB verification IP section, so implementation details are not supported by the supplied evidence. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi