Overview

AHB Verification IP is referenced in the provided evidence as a distinct subsection, "4.2.4 AHB verification IP," in the paper/thesis "UVM based design verification of a RISC-V CPU core." The table of contents places this subsection on page 51, within a larger verification-environment discussion that also includes a scoreboard, the Spike instruction set simulator, and a coverage model.

Role in the cited RISC-V verification work

The available evidence supports only that AHB Verification IP is part of the verification material described in the RISC-V CPU-core verification work. Its placement near sections titled Scoreboard, Spike instruction set simulator, and Coverage model indicates that it is discussed as one element of the verification setup in that work.

Evidence limitations

The provided evidence does not include the body text of section 4.2.4. Therefore, details such as the exact architecture, protocol behavior, UVM component hierarchy, supported transactions, checking strategy, or coverage collected by the AHB Verification IP are not supported by the supplied evidence and are not asserted here.

Related work

• UVM Based Design Verification of a RISC-V CPU Core — the provided evidence shows this work contains a section titled AHB verification IP.