Dhrystone

Concept

Dhrystone is treated in the provided sources as a CPU performance benchmark, commonly grouped with other benchmark workloads such as CoreMark, SPECint, and lmbench. In RISC-V studies, it is used to report throughput and per-MHz efficiency metrics such as DMIPS/MHz, and it appears in verification-oriented evaluation plans for assessing processor performance aspects and bottlenecks.

First seen 5/27/2026

Last seen 5/28/2026

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WIKI

Overview

Dhrystone is a CPU performance benchmark. In verification planning for CPU designs, the provided evidence lists Dhrystone among the patterns or benchmarks used to measure processor performance aspects and identify bottlenecks, alongside examples such as SPECint and lmbench. [C1]

Dhrystone is also used in RISC-V processor evaluation flows. A UVM-based RISC-V CPU verification thesis includes a benchmark section in its experimental evaluation with subsections for Dhrystone and CoreMark. [C2]

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RELATIONSHIPS

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UVM Based Design Verification of a RISC-V CPU Core ← evaluates 95% 1e

The paper evaluates the RISC-V core using the Dhrystone benchmark.

Benchmarks part of → 95% 1e

Dhrystone is one of the benchmarks used in the evaluation.

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UVM Based Design Verification of a RISC-V CPU Core EVALUATES Extracted graph relationship

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CITATIONS

4 sources

4 citations — click to collapse

[1] Dhrystone is listed as a benchmark or benchmark pattern used in CPU performance verification plans to measure performance aspects and bottlenecks. UVM based design verification of a RISC-V CPU core - POLITesi

[2] A UVM-based RISC-V CPU verification thesis includes Dhrystone under the Benchmarks section of its experimental evaluation, alongside CoreMark. UVM based design verification of a RISC-V CPU core - POLITesi

[3] The RV-IM100 public arXiv summary reports Dhrystone throughput and DMIPS/MHz results across RISC-V microarchitectural variants, including effects of IM extension, pipeline deepening, and RV32/RV64 comparison. RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures

[4] The BASIC_RV32s public arXiv summary reports a Dhrystone result of 1.09 DMIPS/MHz at 50 MHz for an RV32I SoC on a Xilinx Artix-7 FPGA. basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I