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Dhrystone

Concept WIKI v1 · 5/27/2026

Dhrystone is treated in the provided sources as a CPU performance benchmark, commonly grouped with other benchmark workloads such as CoreMark, SPECint, and lmbench. In RISC-V studies, it is used to report throughput and per-MHz efficiency metrics such as DMIPS/MHz, and it appears in verification-oriented evaluation plans for assessing processor performance aspects and bottlenecks.

Overview

Dhrystone is a CPU performance benchmark. In verification planning for CPU designs, the provided evidence lists Dhrystone among the patterns or benchmarks used to measure processor performance aspects and identify bottlenecks, alongside examples such as SPECint and lmbench. [C1]

Dhrystone is also used in RISC-V processor evaluation flows. A UVM-based RISC-V CPU verification thesis includes a benchmark section in its experimental evaluation with subsections for Dhrystone and CoreMark. [C2]

Reported metrics and uses

The public RISC-V literature in the provided context reports Dhrystone results both as throughput and as normalized efficiency. For example, the RV-IM100 study compares Dhrystone throughput across RISC-V microarchitectural variants while varying ISA extension, datapath width, and pipeline depth; it reports that, in one RV32IM pipeline-deepening experiment, increasing maximum frequency from 43 MHz to 126 MHz raised both Dhrystone and CoreMark throughput by 71%, while per-MHz efficiency decreased by 41%. [C3]

The same RV-IM100 summary also reports Dhrystone-specific differences across design choices: adding the IM extension at the 5-stage level had benchmark-dependent effects, with CoreMark throughput more than doubling while Dhrystone throughput decreased marginally despite improved per-MHz efficiency; and in an RV32/RV64 comparison, RV64 led by 2.3% in DMIPS/MHz while RV32 led by 4.6% in CoreMark/MHz. [C3]

Another RISC-V implementation report, BASIC_RV32s, uses Dhrystone as an FPGA validation metric, reporting 1.09 DMIPS/MHz at 50 MHz for a final RV32I SoC design on a Xilinx Artix-7 FPGA. [C4]

Relationship to benchmarking

Within the supplied evidence, Dhrystone is best characterized as part of the broader category of processor benchmarks: it appears in benchmark-oriented experimental evaluation and in performance verification plans intended to assess CPU performance behavior. [C1][C2]

LINKED ENTITIES

2 links
UVM Based Design Verification of a RISC-V CPU Core EVALUATES
Benchmarks PART_OF

CITATIONS

4 sources
4 citations
[1] Dhrystone is listed as a benchmark or benchmark pattern used in CPU performance verification plans to measure performance aspects and bottlenecks. UVM based design verification of a RISC-V CPU core - POLITesi
[2] A UVM-based RISC-V CPU verification thesis includes Dhrystone under the Benchmarks section of its experimental evaluation, alongside CoreMark. UVM based design verification of a RISC-V CPU core - POLITesi
[3] The RV-IM100 public arXiv summary reports Dhrystone throughput and DMIPS/MHz results across RISC-V microarchitectural variants, including effects of IM extension, pipeline deepening, and RV32/RV64 comparison. RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
[4] The BASIC_RV32s public arXiv summary reports a Dhrystone result of 1.09 DMIPS/MHz at 50 MHz for an RV32I SoC on a Xilinx Artix-7 FPGA. basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I