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CoreMark

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CoreMark® is an industry-standard benchmark used to measure the performance of CPUs and embedded microcontrollers (MCUs). It is implemented as a portable C codebase maintained as an open-source project, and it is widely adopted as a real-world benchmark alongside other suites such as Dhrystone in processor and SoC verification flows.

First seen 6/25/2026
Last seen 6/25/2026
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Overview

CoreMark® is a benchmark designed to measure the performance of central processing units (CPU) and embedded microcontrollers (MCU) [source: eembc/coremark repository summary]. It is maintained as an open-source C project and is recognized as an industry-standard benchmark for evaluating processor and MCU performance.

Implementation

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RELATIONSHIPS

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Real-world benchmarks implements → 88% 1e
Performance assessment includes running CoreMark as part of real-world benchmarking.

CITATIONS

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4 citations — click to collapse
[1] CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcontrollers (MCU). eembc/coremark
[2] The official CoreMark source is maintained as a C-language project on GitHub under the eembc/coremark repository (1,209 stars, 410 forks, last updated 2026-06-22). eembc/coremark
[3] In the NaxRiscv lockstep verification methodology, CoreMark and Dhrystone are used as real-world benchmarks to assess performance and software–hardware integration after directed compliance tests, alongside OS boot sequences ranging from FreeRTOS to the Linux boot stage. Comprehensive lockstep verification for NaxRiscv SoC integrating ...
[4] The NaxRiscv verification flow combines real-world benchmarks such as CoreMark with riscv-tests/riscv-arch-tests compliance suites, RISCV-DV constrained-random testing, and UVM-based functional coverage reported via vcover. Comprehensive lockstep verification for NaxRiscv SoC integrating ...