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CoreMark

CodeArtifact WIKI v1 · 6/25/2026

CoreMark® is an industry-standard benchmark used to measure the performance of CPUs and embedded microcontrollers (MCUs). It is implemented as a portable C codebase maintained as an open-source project, and it is widely adopted as a real-world benchmark alongside other suites such as Dhrystone in processor and SoC verification flows.

Overview

CoreMark® is a benchmark designed to measure the performance of central processing units (CPU) and embedded microcontrollers (MCU) [source: eembc/coremark repository summary]. It is maintained as an open-source C project and is recognized as an industry-standard benchmark for evaluating processor and MCU performance.

Implementation

The official CoreMark codebase is hosted in the eembc/coremark repository on GitHub. At the time of capture, the project was written in C, had 1,209 stars and 410 forks, and was last updated on 2026-06-22. The repository description states: "CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcontrollers (MCU)."

Use in real-world benchmarking

CoreMark is commonly grouped under "real-world benchmarks" in modern processor and SoC verification methodologies. In the lockstep verification methodology described for the NaxRiscv SoC (a superscalar RISC-V core supporting RV32/64IMAFDC, capable of running Linux and FreeRTOS, and prototyped on FPGA via the LiTeX framework), real-world benchmarks are executed after directed compliance tests to assess performance and software–hardware integration. The methodology explicitly cites CoreMark and Dhrystone as the performance metrics used in this phase, in addition to executing operating-system boot sequences ranging from FreeRTOS to the Linux boot stage [source: NaxRiscv lockstep verification paper].

In that workflow, CoreMark therefore serves as one of the application-level workloads that complement:

  • Compliance suites — riscv-tests and riscv-arch-tests executed in a Jenkins CI pipeline.
  • Constrained-random testing — generated with RISCV-DV to target edge cases such as misaligned instructions, register dependencies, pipeline hazards, memory access violations, and unhandled interrupts.
  • Functional coverage — collected in a UCDB file and reported via vcover report, with coverpoints for operand registers, branch outcomes, and memory alignment.

This combination ensures verification coverage from basic ISA compliance through to resilience under realistic workloads such as CoreMark.

See also

LINKED ENTITIES

1 links
Real-world benchmarks IMPLEMENTS

CITATIONS

4 sources
4 citations
[1] CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcontrollers (MCU). eembc/coremark
[2] The official CoreMark source is maintained as a C-language project on GitHub under the eembc/coremark repository (1,209 stars, 410 forks, last updated 2026-06-22). eembc/coremark
[3] In the NaxRiscv lockstep verification methodology, CoreMark and Dhrystone are used as real-world benchmarks to assess performance and software–hardware integration after directed compliance tests, alongside OS boot sequences ranging from FreeRTOS to the Linux boot stage. Comprehensive lockstep verification for NaxRiscv SoC integrating ...
[4] The NaxRiscv verification flow combines real-world benchmarks such as CoreMark with riscv-tests/riscv-arch-tests compliance suites, RISCV-DV constrained-random testing, and UVM-based functional coverage reported via vcover. Comprehensive lockstep verification for NaxRiscv SoC integrating ...