Verification Test Plan

Concept

A verification test plan is a specification document used in hardware design verification to define what features, configurations, scenarios, coverage goals, stimulus, and checking mechanisms are needed to verify a design under test.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

A Verification Test Plan is a specification document that captures the details needed to verify a given hardware design. It is typically developed by a verification engineer who understands the Design Under Test (DUT), and it is used to plan verification work so that verification can be completed with high quality and within a predictable time period.

A test plan starts from the design specification, also called an architecture or microarchitecture specification. That specification acts as the golden reference for verification and should describe the design implementation, supported features, interfaces and protocols, configuration and initialization information including registers, and other relevant details.

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UVM Based Design Verification of a RISC-V CPU Core ← uses 90% 1e

The paper discusses and employs a verification test plan as part of the verification infrastructure.

Design Under Test uses → 90% 1e

A verification test plan is created to verify a specific design under test.

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CITATIONS

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[1] A verification test plan is a specification document capturing the details needed to verify a design, developed by a verification engineer based on understanding the DUT. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] A test plan starts from the architecture or microarchitecture design specification, which acts as the golden reference and includes features, interfaces, protocols, configuration, initialization, registers, and other design details. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The plan should list features and supported configurations as test-plan items, and many features or configurations may be verified in combination rather than through individual tests. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] A verification test plan may include microarchitectural cases, interface properties, internal events such as state machines, FIFOs and arbitration, block interactions, stimulus patterns, high-level scenarios, and potential deadlock or livelock conditions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] Functional verification commonly uses simulation with constrained-random or coverage-driven approaches, while selected areas may use formal verification or other techniques. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] The plan should document stimulus infrastructure, randomization controls, sequences, tests, and checking mechanisms such as scoreboards or assertions, as well as testbench components, hierarchy, and stimulus patterns. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] For CPU verification, multiple plans may be needed, including architecture verification, microarchitecture verification, and performance verification plans. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] In the Ibex RISC-V example, the testbench executes memory-resident programs, compares the core trace against a Spike ISS trace, collects instruction and operand coverage, and uses test and coverage plans for relevant instructions and operations. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[9] The Ibex test-plan scope includes RV32IMCB instructions, privileged specification compliance, exception and interrupt testing, and Debug Mode operation, with co-simulation against Spike in lockstep. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi