RISC-V Formal Interface (RVFI)
ConceptThe RISC-V Formal Interface (RVFI) is used in RISC-V verification flows to provide checking information about retired instructions and instructions that produce synchronous traps, including in co-simulation setups.
First seen 5/28/2026
Last seen 7/12/2026
Evidence 6 chunks
Wiki v1
WIKI
Overview
The RISC-V Formal Interface (RVFI) is a verification-facing interface used to expose instruction-level information for checking RISC-V processor behavior. In the provided evidence, RVFI is described as providing information about retired instructions and about instructions that produce synchronous traps.
Role in co-simulation
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
5 connectionsRVFI is part of the riscv-formal framework and is used for formal verification of RISC-V processors.
The voter in the paper's approach is based on RVFI to observe processor execution state.
The voter uses RVFI signals to detect mismatches between ISS and RTL processor.
The RVFI Agent uses the RISC-V Formal Interface to monitor processor behavior.
cv32e40p exposes RISC-V Formal Interface signals used by the RVFI Agent.
CITATIONS
2 sources2 citations — click to collapse
[1] RVFI is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The cited co-simulation system requires a particular version of Spike. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi