co-simulation methodology

Concept

In the provided RISC-V verification evidence, co-simulation methodology is a dynamic verification approach that runs an RTL CPU core alongside an instruction-set simulator reference model, such as Spike, and cross-checks instruction execution, memory transactions, and trace logs to detect mismatches.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

In the RISC-V CPU verification context shown by the Ibex testbench, co-simulation methodology refers to running a design under test, such as an RTL CPU core, together with a reference instruction-set simulator (ISS) and comparing their behavior. The Ibex UVM testbench uses this methodology to cross-check Ibex execution against the Spike ISS reference model. [C1]

How it is used in Ibex verification

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CITATIONS

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8 citations — click to expand

[1] Ibex uses a UVM-based testbench employing co-simulation to cross-check execution against the Spike ISS reference model. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The Ibex testbench executes programs from memory, compares the core trace log against a Spike golden-model trace log, and collects coverage for executed instructions and operands. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The Ibex co-simulation system can run in the Ibex UVM DV environment or with Simple System, running a RISC-V ISS in lockstep with Ibex and checking executed instructions and memory transactions against the ISS. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] The co-simulation system supports memory errors, interrupt requests, and debug requests by observing them in RTL simulation and forwarding them to the ISS to keep the RTL and ISS in sync. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] RVFI is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] The co-simulation system currently supports only Spike as its ISS and requires a particular version of Spike, while using a generic interface intended to support multiple ISSes. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] Only VCS is supported as a simulator for the co-simulation system, although no VCS-specific functionality is required and adding another simulator should be straightforward. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] The Ibex verification flow runs binaries built from RISC-DV-generated source and adds randomized memory timings, memory errors, interrupts, and debug requests, with a comprehensive test plan and coverage plan. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi